Bug
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Ошибка # 187
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{ 20 typedef unsigned char __u8; 23 typedef unsigned short __u16; 25 typedef int __s32; 26 typedef unsigned int __u32; 29 typedef long long __s64; 30 typedef unsigned long long __u64; 15 typedef signed char s8; 16 typedef unsigned char u8; 18 typedef short s16; 19 typedef unsigned short u16; 21 typedef int s32; 22 typedef unsigned int u32; 24 typedef long long s64; 25 typedef unsigned long long u64; 14 typedef long __kernel_long_t; 15 typedef unsigned long __kernel_ulong_t; 27 typedef int __kernel_pid_t; 48 typedef unsigned int __kernel_uid32_t; 49 typedef unsigned int __kernel_gid32_t; 71 typedef __kernel_ulong_t __kernel_size_t; 72 typedef __kernel_long_t __kernel_ssize_t; 87 typedef long long __kernel_loff_t; 88 typedef __kernel_long_t __kernel_time_t; 89 typedef __kernel_long_t __kernel_clock_t; 90 typedef int __kernel_timer_t; 91 typedef int __kernel_clockid_t; 287 struct kernel_symbol { unsigned long value; const char *name; } ; 34 struct module ; 12 typedef __u32 __kernel_dev_t; 15 typedef __kernel_dev_t dev_t; 18 typedef unsigned short umode_t; 21 typedef __kernel_pid_t pid_t; 26 typedef __kernel_clockid_t clockid_t; 29 typedef _Bool bool; 31 typedef __kernel_uid32_t uid_t; 32 typedef __kernel_gid32_t gid_t; 45 typedef __kernel_loff_t loff_t; 54 typedef __kernel_size_t size_t; 59 typedef __kernel_ssize_t ssize_t; 69 typedef __kernel_time_t time_t; 102 typedef __s32 int32_t; 108 typedef __u32 uint32_t; 133 typedef unsigned long sector_t; 134 typedef unsigned long blkcnt_t; 157 typedef unsigned int gfp_t; 158 typedef unsigned int fmode_t; 161 typedef u64 phys_addr_t; 166 typedef phys_addr_t resource_size_t; 176 struct __anonstruct_atomic_t_6 { int counter; } ; 176 typedef struct __anonstruct_atomic_t_6 atomic_t; 181 struct __anonstruct_atomic64_t_7 { long counter; } ; 181 typedef struct __anonstruct_atomic64_t_7 atomic64_t; 182 struct list_head { struct list_head *next; struct list_head *prev; } ; 187 struct hlist_node ; 187 struct hlist_head { struct hlist_node *first; } ; 191 struct hlist_node { struct hlist_node *next; struct hlist_node **pprev; } ; 202 struct callback_head { struct callback_head *next; void (*func)(struct callback_head *); } ; 117 typedef void (*ctor_fn_t)(); 283 struct _ddebug { const char *modname; const char *function; const char *filename; const char *format; unsigned int lineno; unsigned char flags; } ; 58 struct device ; 474 struct file_operations ; 486 struct completion ; 487 struct pt_regs ; 546 struct bug_entry { int bug_addr_disp; int file_disp; unsigned short line; unsigned short flags; } ; 61 struct timespec ; 62 struct compat_timespec ; 63 struct pollfd ; 64 enum timespec_type { TT_NONE = 0, TT_NATIVE = 1, TT_COMPAT = 2 } ; 70 struct __anonstruct_futex_27 { u32 *uaddr; u32 val; u32 flags; u32 bitset; u64 time; u32 *uaddr2; } ; 70 union __anonunion____missing_field_name_29 { struct timespec *rmtp; struct compat_timespec *compat_rmtp; } ; 70 struct __anonstruct_nanosleep_28 { clockid_t clockid; enum timespec_type type; union __anonunion____missing_field_name_29 __annonCompField4; u64 expires; } ; 70 struct __anonstruct_poll_30 { struct pollfd *ufds; int nfds; int has_timeout; unsigned long tv_sec; unsigned long tv_nsec; } ; 70 union __anonunion____missing_field_name_26 { struct __anonstruct_futex_27 futex; struct __anonstruct_nanosleep_28 nanosleep; struct __anonstruct_poll_30 poll; } ; 70 struct restart_block { long int (*fn)(struct restart_block *); union __anonunion____missing_field_name_26 __annonCompField5; } ; 61 struct task_struct ; 53 struct page ; 26 struct mm_struct ; 288 struct pt_regs { unsigned long r15; unsigned long r14; unsigned long r13; unsigned long r12; unsigned long bp; unsigned long bx; unsigned long r11; unsigned long r10; unsigned long r9; unsigned long r8; unsigned long ax; unsigned long cx; unsigned long dx; unsigned long si; unsigned long di; unsigned long orig_ax; unsigned long ip; unsigned long cs; unsigned long flags; unsigned long sp; unsigned long ss; } ; 66 struct __anonstruct____missing_field_name_33 { unsigned int a; unsigned int b; } ; 66 struct __anonstruct____missing_field_name_34 { u16 limit0; u16 base0; unsigned char base1; unsigned char type; unsigned char s; unsigned char dpl; unsigned char p; unsigned char limit; unsigned char avl; unsigned char l; unsigned char d; unsigned char g; unsigned char base2; } ; 66 union __anonunion____missing_field_name_32 { struct __anonstruct____missing_field_name_33 __annonCompField6; struct __anonstruct____missing_field_name_34 __annonCompField7; } ; 66 struct desc_struct { union __anonunion____missing_field_name_32 __annonCompField8; } ; 17 typedef unsigned long pgdval_t; 18 typedef unsigned long pgprotval_t; 22 struct pgprot { pgprotval_t pgprot; } ; 256 typedef struct pgprot pgprot_t; 258 struct __anonstruct_pgd_t_36 { pgdval_t pgd; } ; 258 typedef struct __anonstruct_pgd_t_36 pgd_t; 460 typedef struct page *pgtable_t; 471 struct file ; 482 struct seq_file ; 519 struct thread_struct ; 521 struct cpumask ; 20 struct qspinlock { atomic_t val; } ; 33 typedef struct qspinlock arch_spinlock_t; 34 struct qrwlock { atomic_t cnts; arch_spinlock_t wait_lock; } ; 14 typedef struct qrwlock arch_rwlock_t; 247 struct math_emu_info { long ___orig_eip; struct pt_regs *regs; } ; 83 struct static_key { atomic_t enabled; } ; 23 typedef atomic64_t atomic_long_t; 380 struct cpumask { unsigned long bits[128U]; } ; 15 typedef struct cpumask cpumask_t; 685 typedef struct cpumask *cpumask_var_t; 22 struct tracepoint_func { void *func; void *data; int prio; } ; 28 struct tracepoint { const char *name; struct static_key key; int (*regfunc)(); void (*unregfunc)(); struct tracepoint_func *funcs; } ; 237 struct fregs_state { u32 cwd; u32 swd; u32 twd; u32 fip; u32 fcs; u32 foo; u32 fos; u32 st_space[20U]; u32 status; } ; 26 struct __anonstruct____missing_field_name_63 { u64 rip; u64 rdp; } ; 26 struct __anonstruct____missing_field_name_64 { u32 fip; u32 fcs; u32 foo; u32 fos; } ; 26 union __anonunion____missing_field_name_62 { struct __anonstruct____missing_field_name_63 __annonCompField14; struct __anonstruct____missing_field_name_64 __annonCompField15; } ; 26 union __anonunion____missing_field_name_65 { u32 padding1[12U]; u32 sw_reserved[12U]; } ; 26 struct fxregs_state { u16 cwd; u16 swd; u16 twd; u16 fop; union __anonunion____missing_field_name_62 __annonCompField16; u32 mxcsr; u32 mxcsr_mask; u32 st_space[32U]; u32 xmm_space[64U]; u32 padding[12U]; union __anonunion____missing_field_name_65 __annonCompField17; } ; 66 struct swregs_state { u32 cwd; u32 swd; u32 twd; u32 fip; u32 fcs; u32 foo; u32 fos; u32 st_space[20U]; u8 ftop; u8 changed; u8 lookahead; u8 no_update; u8 rm; u8 alimit; struct math_emu_info *info; u32 entry_eip; } ; 227 struct xstate_header { u64 xfeatures; u64 xcomp_bv; u64 reserved[6U]; } ; 233 struct xregs_state { struct fxregs_state i387; struct xstate_header header; u8 extended_state_area[0U]; } ; 254 union fpregs_state { struct fregs_state fsave; struct fxregs_state fxsave; struct swregs_state soft; struct xregs_state xsave; u8 __padding[4096U]; } ; 271 struct fpu { unsigned int last_cpu; unsigned char fpstate_active; unsigned char fpregs_active; union fpregs_state state; } ; 174 struct seq_operations ; 416 struct perf_event ; 421 struct __anonstruct_mm_segment_t_77 { unsigned long seg; } ; 421 typedef struct __anonstruct_mm_segment_t_77 mm_segment_t; 422 struct thread_struct { struct desc_struct tls_array[3U]; unsigned long sp0; unsigned long sp; unsigned short es; unsigned short ds; unsigned short fsindex; unsigned short gsindex; u32 status; unsigned long fsbase; unsigned long gsbase; struct perf_event *ptrace_bps[4U]; unsigned long debugreg6; unsigned long ptrace_dr7; unsigned long cr2; unsigned long trap_nr; unsigned long error_code; unsigned long *io_bitmap_ptr; unsigned long iopl; unsigned int io_bitmap_max; mm_segment_t addr_limit; unsigned char sig_on_uaccess_err; unsigned char uaccess_err; struct fpu fpu; } ; 48 struct thread_info { unsigned long flags; } ; 33 struct lockdep_map ; 55 struct stack_trace { unsigned int nr_entries; unsigned int max_entries; unsigned long *entries; int skip; } ; 30 struct lockdep_subclass_key { char __one_byte; } ; 53 struct lock_class_key { struct lockdep_subclass_key subkeys[8U]; } ; 59 struct lock_class { struct hlist_node hash_entry; struct list_head lock_entry; struct lockdep_subclass_key *key; unsigned int subclass; unsigned int dep_gen_id; unsigned long usage_mask; struct stack_trace usage_traces[13U]; struct list_head locks_after; struct list_head locks_before; unsigned int version; unsigned long ops; const char *name; int name_version; unsigned long contention_point[4U]; unsigned long contending_point[4U]; } ; 144 struct lockdep_map { struct lock_class_key *key; struct lock_class *class_cache[2U]; const char *name; int cpu; unsigned long ip; } ; 207 struct held_lock { u64 prev_chain_key; unsigned long acquire_ip; struct lockdep_map *instance; struct lockdep_map *nest_lock; u64 waittime_stamp; u64 holdtime_stamp; unsigned short class_idx; unsigned char irq_context; unsigned char trylock; unsigned char read; unsigned char check; unsigned char hardirqs_off; unsigned short references; unsigned int pin_count; } ; 596 struct raw_spinlock { arch_spinlock_t raw_lock; unsigned int magic; unsigned int owner_cpu; void *owner; struct lockdep_map dep_map; } ; 32 typedef struct raw_spinlock raw_spinlock_t; 33 struct __anonstruct____missing_field_name_79 { u8 __padding[24U]; struct lockdep_map dep_map; } ; 33 union __anonunion____missing_field_name_78 { struct raw_spinlock rlock; struct __anonstruct____missing_field_name_79 __annonCompField20; } ; 33 struct spinlock { union __anonunion____missing_field_name_78 __annonCompField21; } ; 76 typedef struct spinlock spinlock_t; 23 struct __anonstruct_rwlock_t_80 { arch_rwlock_t raw_lock; unsigned int magic; unsigned int owner_cpu; void *owner; struct lockdep_map dep_map; } ; 23 typedef struct __anonstruct_rwlock_t_80 rwlock_t; 428 struct seqcount { unsigned int sequence; struct lockdep_map dep_map; } ; 52 typedef struct seqcount seqcount_t; 601 struct timespec { __kernel_time_t tv_sec; long tv_nsec; } ; 7 typedef __s64 time64_t; 83 struct user_namespace ; 22 struct __anonstruct_kuid_t_96 { uid_t val; } ; 22 typedef struct __anonstruct_kuid_t_96 kuid_t; 27 struct __anonstruct_kgid_t_97 { gid_t val; } ; 27 typedef struct __anonstruct_kgid_t_97 kgid_t; 139 struct kstat { u32 result_mask; umode_t mode; unsigned int nlink; uint32_t blksize; u64 attributes; u64 attributes_mask; u64 ino; dev_t dev; dev_t rdev; kuid_t uid; kgid_t gid; loff_t size; struct timespec atime; struct timespec mtime; struct timespec ctime; struct timespec btime; u64 blocks; } ; 49 struct vm_area_struct ; 31 struct wait_queue_head { spinlock_t lock; struct list_head head; } ; 36 typedef struct wait_queue_head wait_queue_head_t; 97 struct __anonstruct_nodemask_t_98 { unsigned long bits[16U]; } ; 97 typedef struct __anonstruct_nodemask_t_98 nodemask_t; 253 typedef unsigned int isolate_mode_t; 13 struct optimistic_spin_queue { atomic_t tail; } ; 39 struct ww_acquire_ctx ; 40 struct mutex { atomic_long_t owner; spinlock_t wait_lock; struct optimistic_spin_queue osq; struct list_head wait_list; void *magic; struct lockdep_map dep_map; } ; 72 struct mutex_waiter { struct list_head list; struct task_struct *task; struct ww_acquire_ctx *ww_ctx; void *magic; } ; 229 struct rw_semaphore ; 230 struct rw_semaphore { atomic_long_t count; struct list_head wait_list; raw_spinlock_t wait_lock; struct optimistic_spin_queue osq; struct task_struct *owner; struct lockdep_map dep_map; } ; 28 typedef s64 ktime_t; 109 struct timer_list { struct hlist_node entry; unsigned long expires; void (*function)(unsigned long); unsigned long data; u32 flags; struct lockdep_map lockdep_map; } ; 211 struct hrtimer ; 212 enum hrtimer_restart ; 235 struct workqueue_struct ; 236 struct work_struct ; 54 struct work_struct { atomic_long_t data; struct list_head entry; void (*func)(struct work_struct *); struct lockdep_map lockdep_map; } ; 107 struct delayed_work { struct work_struct work; struct timer_list timer; struct workqueue_struct *wq; int cpu; } ; 42 struct completion { unsigned int done; wait_queue_head_t wait; } ; 217 struct resource ; 38 struct ldt_struct ; 38 struct vdso_image ; 38 struct __anonstruct_mm_context_t_163 { struct ldt_struct *ldt; unsigned short ia32_compat; struct mutex lock; void *vdso; const struct vdso_image *vdso_image; atomic_t perf_rdpmc_allowed; u16 pkey_allocation_map; s16 execute_only_pkey; void *bd_addr; } ; 38 typedef struct __anonstruct_mm_context_t_163 mm_context_t; 1314 struct llist_node ; 1314 struct llist_head { struct llist_node *first; } ; 69 struct llist_node { struct llist_node *next; } ; 596 struct rb_node { unsigned long __rb_parent_color; struct rb_node *rb_right; struct rb_node *rb_left; } ; 41 struct rb_root { struct rb_node *rb_node; } ; 836 struct nsproxy ; 37 struct cred ; 19 struct arch_tlbflush_unmap_batch { struct cpumask cpumask; } ; 13 struct vmacache { u32 seqnum; struct vm_area_struct *vmas[4U]; } ; 45 struct task_rss_stat { int events; int count[4U]; } ; 53 struct mm_rss_stat { atomic_long_t count[4U]; } ; 58 struct page_frag { struct page *page; __u32 offset; __u32 size; } ; 65 struct tlbflush_unmap_batch { struct arch_tlbflush_unmap_batch arch; bool flush_required; bool writable; } ; 92 struct inode ; 58 struct arch_uprobe_task { unsigned long saved_scratch_register; unsigned int saved_trap_nr; unsigned int saved_tf; } ; 66 enum uprobe_task_state { UTASK_RUNNING = 0, UTASK_SSTEP = 1, UTASK_SSTEP_ACK = 2, UTASK_SSTEP_TRAPPED = 3 } ; 73 struct __anonstruct____missing_field_name_217 { struct arch_uprobe_task autask; unsigned long vaddr; } ; 73 struct __anonstruct____missing_field_name_218 { struct callback_head dup_xol_work; unsigned long dup_xol_addr; } ; 73 union __anonunion____missing_field_name_216 { struct __anonstruct____missing_field_name_217 __annonCompField36; struct __anonstruct____missing_field_name_218 __annonCompField37; } ; 73 struct uprobe ; 73 struct return_instance ; 73 struct uprobe_task { enum uprobe_task_state state; union __anonunion____missing_field_name_216 __annonCompField38; struct uprobe *active_uprobe; unsigned long xol_vaddr; struct return_instance *return_instances; unsigned int depth; } ; 95 struct return_instance { struct uprobe *uprobe; unsigned long func; unsigned long stack; unsigned long orig_ret_vaddr; bool chained; struct return_instance *next; } ; 111 struct xol_area ; 112 struct uprobes_state { struct xol_area *xol_area; } ; 151 struct address_space ; 152 struct mem_cgroup ; 153 union __anonunion____missing_field_name_219 { struct address_space *mapping; void *s_mem; atomic_t compound_mapcount; } ; 153 union __anonunion____missing_field_name_220 { unsigned long index; void *freelist; } ; 153 struct __anonstruct____missing_field_name_224 { unsigned short inuse; unsigned short objects; unsigned char frozen; } ; 153 union __anonunion____missing_field_name_223 { atomic_t _mapcount; unsigned int active; struct __anonstruct____missing_field_name_224 __annonCompField41; int units; } ; 153 struct __anonstruct____missing_field_name_222 { union __anonunion____missing_field_name_223 __annonCompField42; atomic_t _refcount; } ; 153 union __anonunion____missing_field_name_221 { unsigned long counters; struct __anonstruct____missing_field_name_222 __annonCompField43; } ; 153 struct dev_pagemap ; 153 struct __anonstruct____missing_field_name_226 { struct page *next; int pages; int pobjects; } ; 153 struct __anonstruct____missing_field_name_227 { unsigned long compound_head; unsigned int compound_dtor; unsigned int compound_order; } ; 153 struct __anonstruct____missing_field_name_228 { unsigned long __pad; pgtable_t pmd_huge_pte; } ; 153 union __anonunion____missing_field_name_225 { struct list_head lru; struct dev_pagemap *pgmap; struct __anonstruct____missing_field_name_226 __annonCompField45; struct callback_head callback_head; struct __anonstruct____missing_field_name_227 __annonCompField46; struct __anonstruct____missing_field_name_228 __annonCompField47; } ; 153 struct kmem_cache ; 153 union __anonunion____missing_field_name_229 { unsigned long private; spinlock_t *ptl; struct kmem_cache *slab_cache; } ; 153 struct page { unsigned long flags; union __anonunion____missing_field_name_219 __annonCompField39; union __anonunion____missing_field_name_220 __annonCompField40; union __anonunion____missing_field_name_221 __annonCompField44; union __anonunion____missing_field_name_225 __annonCompField48; union __anonunion____missing_field_name_229 __annonCompField49; struct mem_cgroup *mem_cgroup; } ; 266 struct userfaultfd_ctx ; 266 struct vm_userfaultfd_ctx { struct userfaultfd_ctx *ctx; } ; 273 struct __anonstruct_shared_230 { struct rb_node rb; unsigned long rb_subtree_last; } ; 273 struct anon_vma ; 273 struct vm_operations_struct ; 273 struct mempolicy ; 273 struct vm_area_struct { unsigned long vm_start; unsigned long vm_end; struct vm_area_struct *vm_next; struct vm_area_struct *vm_prev; struct rb_node vm_rb; unsigned long rb_subtree_gap; struct mm_struct *vm_mm; pgprot_t vm_page_prot; unsigned long vm_flags; struct __anonstruct_shared_230 shared; struct list_head anon_vma_chain; struct anon_vma *anon_vma; const struct vm_operations_struct *vm_ops; unsigned long vm_pgoff; struct file *vm_file; void *vm_private_data; struct mempolicy *vm_policy; struct vm_userfaultfd_ctx vm_userfaultfd_ctx; } ; 346 struct core_thread { struct task_struct *task; struct core_thread *next; } ; 351 struct core_state { atomic_t nr_threads; struct core_thread dumper; struct completion startup; } ; 357 struct kioctx_table ; 358 struct linux_binfmt ; 358 struct mmu_notifier_mm ; 358 struct mm_struct { struct vm_area_struct *mmap; struct rb_root mm_rb; u32 vmacache_seqnum; unsigned long int (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); unsigned long mmap_base; unsigned long mmap_legacy_base; unsigned long mmap_compat_base; unsigned long mmap_compat_legacy_base; unsigned long task_size; unsigned long highest_vm_end; pgd_t *pgd; atomic_t mm_users; atomic_t mm_count; atomic_long_t nr_ptes; atomic_long_t nr_pmds; int map_count; spinlock_t page_table_lock; struct rw_semaphore mmap_sem; struct list_head mmlist; unsigned long hiwater_rss; unsigned long hiwater_vm; unsigned long total_vm; unsigned long locked_vm; unsigned long pinned_vm; unsigned long data_vm; unsigned long exec_vm; unsigned long stack_vm; unsigned long def_flags; unsigned long start_code; unsigned long end_code; unsigned long start_data; unsigned long end_data; unsigned long start_brk; unsigned long brk; unsigned long start_stack; unsigned long arg_start; unsigned long arg_end; unsigned long env_start; unsigned long env_end; unsigned long saved_auxv[46U]; struct mm_rss_stat rss_stat; struct linux_binfmt *binfmt; cpumask_var_t cpu_vm_mask_var; mm_context_t context; unsigned long flags; struct core_state *core_state; spinlock_t ioctx_lock; struct kioctx_table *ioctx_table; struct task_struct *owner; struct user_namespace *user_ns; struct file *exe_file; struct mmu_notifier_mm *mmu_notifier_mm; struct cpumask cpumask_allocation; unsigned long numa_next_scan; unsigned long numa_scan_offset; int numa_scan_seq; bool tlb_flush_pending; struct uprobes_state uprobes_state; atomic_long_t hugetlb_usage; struct work_struct async_put_work; } ; 603 struct vdso_image { void *data; unsigned long size; unsigned long alt; unsigned long alt_len; long sym_vvar_start; long sym_vvar_page; long sym_hpet_page; long sym_pvclock_page; long sym_hvclock_page; long sym_VDSO32_NOTE_MASK; long sym___kernel_sigreturn; long sym___kernel_rt_sigreturn; long sym___kernel_vsyscall; long sym_int80_landing_pad; } ; 15 typedef __u64 Elf64_Addr; 16 typedef __u16 Elf64_Half; 18 typedef __u64 Elf64_Off; 20 typedef __u32 Elf64_Word; 21 typedef __u64 Elf64_Xword; 190 struct elf64_sym { Elf64_Word st_name; unsigned char st_info; unsigned char st_other; Elf64_Half st_shndx; Elf64_Addr st_value; Elf64_Xword st_size; } ; 198 typedef struct elf64_sym Elf64_Sym; 219 struct elf64_hdr { unsigned char e_ident[16U]; Elf64_Half e_type; Elf64_Half e_machine; Elf64_Word e_version; Elf64_Addr e_entry; Elf64_Off e_phoff; Elf64_Off e_shoff; Elf64_Word e_flags; Elf64_Half e_ehsize; Elf64_Half e_phentsize; Elf64_Half e_phnum; Elf64_Half e_shentsize; Elf64_Half e_shnum; Elf64_Half e_shstrndx; } ; 235 typedef struct elf64_hdr Elf64_Ehdr; 314 struct elf64_shdr { Elf64_Word sh_name; Elf64_Word sh_type; Elf64_Xword sh_flags; Elf64_Addr sh_addr; Elf64_Off sh_offset; Elf64_Xword sh_size; Elf64_Word sh_link; Elf64_Word sh_info; Elf64_Xword sh_addralign; Elf64_Xword sh_entsize; } ; 326 typedef struct elf64_shdr Elf64_Shdr; 65 struct radix_tree_root ; 65 union __anonunion____missing_field_name_235 { struct list_head private_list; struct callback_head callback_head; } ; 65 struct radix_tree_node { unsigned char shift; unsigned char offset; unsigned char count; unsigned char exceptional; struct radix_tree_node *parent; struct radix_tree_root *root; union __anonunion____missing_field_name_235 __annonCompField50; void *slots[64U]; unsigned long tags[3U][1U]; } ; 107 struct radix_tree_root { gfp_t gfp_mask; struct radix_tree_node *rnode; } ; 176 struct ida { struct radix_tree_root ida_rt; } ; 216 struct dentry ; 217 struct iattr ; 218 struct super_block ; 219 struct file_system_type ; 220 struct kernfs_open_node ; 221 struct kernfs_iattrs ; 245 struct kernfs_root ; 245 struct kernfs_elem_dir { unsigned long subdirs; struct rb_root children; struct kernfs_root *root; } ; 86 struct kernfs_node ; 86 struct kernfs_elem_symlink { struct kernfs_node *target_kn; } ; 90 struct kernfs_ops ; 90 struct kernfs_elem_attr { const struct kernfs_ops *ops; struct kernfs_open_node *open; loff_t size; struct kernfs_node *notify_next; } ; 97 union __anonunion____missing_field_name_244 { struct kernfs_elem_dir dir; struct kernfs_elem_symlink symlink; struct kernfs_elem_attr attr; } ; 97 struct kernfs_node { atomic_t count; atomic_t active; struct lockdep_map dep_map; struct kernfs_node *parent; const char *name; struct rb_node rb; const void *ns; unsigned int hash; union __anonunion____missing_field_name_244 __annonCompField51; void *priv; unsigned short flags; umode_t mode; unsigned int ino; struct kernfs_iattrs *iattr; } ; 139 struct kernfs_syscall_ops { int (*remount_fs)(struct kernfs_root *, int *, char *); int (*show_options)(struct seq_file *, struct kernfs_root *); int (*mkdir)(struct kernfs_node *, const char *, umode_t ); int (*rmdir)(struct kernfs_node *); int (*rename)(struct kernfs_node *, struct kernfs_node *, const char *); int (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *); } ; 158 struct kernfs_root { struct kernfs_node *kn; unsigned int flags; struct ida ino_ida; struct kernfs_syscall_ops *syscall_ops; struct list_head supers; wait_queue_head_t deactivate_waitq; } ; 174 struct kernfs_open_file { struct kernfs_node *kn; struct file *file; struct seq_file *seq_file; void *priv; struct mutex mutex; struct mutex prealloc_mutex; int event; struct list_head list; char *prealloc_buf; size_t atomic_write_len; bool mmapped; bool released; const struct vm_operations_struct *vm_ops; } ; 194 struct kernfs_ops { int (*open)(struct kernfs_open_file *); void (*release)(struct kernfs_open_file *); int (*seq_show)(struct seq_file *, void *); void * (*seq_start)(struct seq_file *, loff_t *); void * (*seq_next)(struct seq_file *, void *, loff_t *); void (*seq_stop)(struct seq_file *, void *); ssize_t (*read)(struct kernfs_open_file *, char *, size_t , loff_t ); size_t atomic_write_len; bool prealloc; ssize_t (*write)(struct kernfs_open_file *, char *, size_t , loff_t ); int (*mmap)(struct kernfs_open_file *, struct vm_area_struct *); struct lock_class_key lockdep_key; } ; 521 struct sock ; 522 struct kobject ; 523 enum kobj_ns_type { KOBJ_NS_TYPE_NONE = 0, KOBJ_NS_TYPE_NET = 1, KOBJ_NS_TYPES = 2 } ; 529 struct kobj_ns_type_operations { enum kobj_ns_type type; bool (*current_may_mount)(); void * (*grab_current_ns)(); const void * (*netlink_ns)(struct sock *); const void * (*initial_ns)(); void (*drop_ns)(void *); } ; 59 struct bin_attribute ; 60 struct attribute { const char *name; umode_t mode; bool ignore_lockdep; struct lock_class_key *key; struct lock_class_key skey; } ; 37 struct attribute_group { const char *name; umode_t (*is_visible)(struct kobject *, struct attribute *, int); umode_t (*is_bin_visible)(struct kobject *, struct bin_attribute *, int); struct attribute **attrs; struct bin_attribute **bin_attrs; } ; 92 struct bin_attribute { struct attribute attr; size_t size; void *private; ssize_t (*read)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t , size_t ); ssize_t (*write)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t , size_t ); int (*mmap)(struct file *, struct kobject *, struct bin_attribute *, struct vm_area_struct *); } ; 165 struct sysfs_ops { ssize_t (*show)(struct kobject *, struct attribute *, char *); ssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t ); } ; 530 struct refcount_struct { atomic_t refs; } ; 19 typedef struct refcount_struct refcount_t; 96 struct kref { refcount_t refcount; } ; 52 struct kset ; 52 struct kobj_type ; 52 struct kobject { const char *name; struct list_head entry; struct kobject *parent; struct kset *kset; struct kobj_type *ktype; struct kernfs_node *sd; struct kref kref; struct delayed_work release; unsigned char state_initialized; unsigned char state_in_sysfs; unsigned char state_add_uevent_sent; unsigned char state_remove_uevent_sent; unsigned char uevent_suppress; } ; 117 struct kobj_type { void (*release)(struct kobject *); const struct sysfs_ops *sysfs_ops; struct attribute **default_attrs; const struct kobj_ns_type_operations * (*child_ns_type)(struct kobject *); const void * (*namespace)(struct kobject *); } ; 125 struct kobj_uevent_env { char *argv[3U]; char *envp[32U]; int envp_idx; char buf[2048U]; int buflen; } ; 133 struct kset_uevent_ops { const int (*filter)(struct kset *, struct kobject *); const const char * (*name)(struct kset *, struct kobject *); const int (*uevent)(struct kset *, struct kobject *, struct kobj_uevent_env *); } ; 150 struct kset { struct list_head list; spinlock_t list_lock; struct kobject kobj; const struct kset_uevent_ops *uevent_ops; } ; 224 struct kernel_param ; 229 struct kernel_param_ops { unsigned int flags; int (*set)(const char *, const struct kernel_param *); int (*get)(char *, const struct kernel_param *); void (*free)(void *); } ; 63 struct kparam_string ; 63 struct kparam_array ; 63 union __anonunion____missing_field_name_247 { void *arg; const struct kparam_string *str; const struct kparam_array *arr; } ; 63 struct kernel_param { const char *name; struct module *mod; const struct kernel_param_ops *ops; const u16 perm; s8 level; u8 flags; union __anonunion____missing_field_name_247 __annonCompField52; } ; 85 struct kparam_string { unsigned int maxlen; char *string; } ; 91 struct kparam_array { unsigned int max; unsigned int elemsize; unsigned int *num; const struct kernel_param_ops *ops; void *elem; } ; 533 struct latch_tree_node { struct rb_node node[2U]; } ; 211 struct mod_arch_specific { } ; 38 struct exception_table_entry ; 39 struct module_param_attrs ; 39 struct module_kobject { struct kobject kobj; struct module *mod; struct kobject *drivers_dir; struct module_param_attrs *mp; struct completion *kobj_completion; } ; 49 struct module_attribute { struct attribute attr; ssize_t (*show)(struct module_attribute *, struct module_kobject *, char *); ssize_t (*store)(struct module_attribute *, struct module_kobject *, const char *, size_t ); void (*setup)(struct module *, const char *); int (*test)(struct module *); void (*free)(struct module *); } ; 276 enum module_state { MODULE_STATE_LIVE = 0, MODULE_STATE_COMING = 1, MODULE_STATE_GOING = 2, MODULE_STATE_UNFORMED = 3 } ; 283 struct mod_tree_node { struct module *mod; struct latch_tree_node node; } ; 288 struct module_layout { void *base; unsigned int size; unsigned int text_size; unsigned int ro_size; unsigned int ro_after_init_size; struct mod_tree_node mtn; } ; 304 struct mod_kallsyms { Elf64_Sym *symtab; unsigned int num_symtab; char *strtab; } ; 318 struct klp_modinfo { Elf64_Ehdr hdr; Elf64_Shdr *sechdrs; char *secstrings; unsigned int symndx; } ; 326 struct module_sect_attrs ; 326 struct module_notes_attrs ; 326 struct trace_event_call ; 326 struct trace_eval_map ; 326 struct module { enum module_state state; struct list_head list; char name[56U]; struct module_kobject mkobj; struct module_attribute *modinfo_attrs; const char *version; const char *srcversion; struct kobject *holders_dir; const struct kernel_symbol *syms; const s32 *crcs; unsigned int num_syms; struct mutex param_lock; struct kernel_param *kp; unsigned int num_kp; unsigned int num_gpl_syms; const struct kernel_symbol *gpl_syms; const s32 *gpl_crcs; const struct kernel_symbol *unused_syms; const s32 *unused_crcs; unsigned int num_unused_syms; unsigned int num_unused_gpl_syms; const struct kernel_symbol *unused_gpl_syms; const s32 *unused_gpl_crcs; bool sig_ok; bool async_probe_requested; const struct kernel_symbol *gpl_future_syms; const s32 *gpl_future_crcs; unsigned int num_gpl_future_syms; unsigned int num_exentries; struct exception_table_entry *extable; int (*init)(); struct module_layout core_layout; struct module_layout init_layout; struct mod_arch_specific arch; unsigned long taints; unsigned int num_bugs; struct list_head bug_list; struct bug_entry *bug_table; struct mod_kallsyms *kallsyms; struct mod_kallsyms core_kallsyms; struct module_sect_attrs *sect_attrs; struct module_notes_attrs *notes_attrs; char *args; void *percpu; unsigned int percpu_size; unsigned int num_tracepoints; const struct tracepoint **tracepoints_ptrs; unsigned int num_trace_bprintk_fmt; const char **trace_bprintk_fmt_start; struct trace_event_call **trace_events; unsigned int num_trace_events; struct trace_eval_map **trace_evals; unsigned int num_trace_evals; bool klp; bool klp_alive; struct klp_modinfo *klp_info; struct list_head source_list; struct list_head target_list; void (*exit)(); atomic_t refcnt; ctor_fn_t (**ctors)(); unsigned int num_ctors; } ; 802 struct clk ; 13 struct device_node ; 690 struct resource { resource_size_t start; resource_size_t end; const char *name; unsigned long flags; unsigned long desc; struct resource *parent; struct resource *sibling; struct resource *child; } ; 282 struct klist_node ; 37 struct klist_node { void *n_klist; struct list_head n_node; struct kref n_ref; } ; 93 struct hlist_bl_node ; 93 struct hlist_bl_head { struct hlist_bl_node *first; } ; 36 struct hlist_bl_node { struct hlist_bl_node *next; struct hlist_bl_node **pprev; } ; 114 struct __anonstruct____missing_field_name_301 { spinlock_t lock; int count; } ; 114 union __anonunion____missing_field_name_300 { struct __anonstruct____missing_field_name_301 __annonCompField53; } ; 114 struct lockref { union __anonunion____missing_field_name_300 __annonCompField54; } ; 77 struct path ; 78 struct vfsmount ; 79 struct __anonstruct____missing_field_name_303 { u32 hash; u32 len; } ; 79 union __anonunion____missing_field_name_302 { struct __anonstruct____missing_field_name_303 __annonCompField55; u64 hash_len; } ; 79 struct qstr { union __anonunion____missing_field_name_302 __annonCompField56; const unsigned char *name; } ; 71 struct dentry_operations ; 71 union __anonunion____missing_field_name_304 { struct list_head d_lru; wait_queue_head_t *d_wait; } ; 71 union __anonunion_d_u_305 { struct hlist_node d_alias; struct hlist_bl_node d_in_lookup_hash; struct callback_head d_rcu; } ; 71 struct dentry { unsigned int d_flags; seqcount_t d_seq; struct hlist_bl_node d_hash; struct dentry *d_parent; struct qstr d_name; struct inode *d_inode; unsigned char d_iname[32U]; struct lockref d_lockref; const struct dentry_operations *d_op; struct super_block *d_sb; unsigned long d_time; void *d_fsdata; union __anonunion____missing_field_name_304 __annonCompField57; struct list_head d_child; struct list_head d_subdirs; union __anonunion_d_u_305 d_u; } ; 127 struct dentry_operations { int (*d_revalidate)(struct dentry *, unsigned int); int (*d_weak_revalidate)(struct dentry *, unsigned int); int (*d_hash)(const struct dentry *, struct qstr *); int (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *); int (*d_delete)(const struct dentry *); int (*d_init)(struct dentry *); void (*d_release)(struct dentry *); void (*d_prune)(struct dentry *); void (*d_iput)(struct dentry *, struct inode *); char * (*d_dname)(struct dentry *, char *, int); struct vfsmount * (*d_automount)(struct path *); int (*d_manage)(const struct path *, bool ); struct dentry * (*d_real)(struct dentry *, const struct inode *, unsigned int); } ; 605 struct path { struct vfsmount *mnt; struct dentry *dentry; } ; 19 struct shrink_control { gfp_t gfp_mask; unsigned long nr_to_scan; int nid; struct mem_cgroup *memcg; } ; 27 struct shrinker { unsigned long int (*count_objects)(struct shrinker *, struct shrink_control *); unsigned long int (*scan_objects)(struct shrinker *, struct shrink_control *); int seeks; long batch; unsigned long flags; struct list_head list; atomic_long_t *nr_deferred; } ; 80 struct list_lru_one { struct list_head list; long nr_items; } ; 32 struct list_lru_memcg { struct list_lru_one *lru[0U]; } ; 37 struct list_lru_node { spinlock_t lock; struct list_lru_one lru; struct list_lru_memcg *memcg_lrus; long nr_items; } ; 49 struct list_lru { struct list_lru_node *node; struct list_head list; } ; 190 enum pid_type { PIDTYPE_PID = 0, PIDTYPE_PGID = 1, PIDTYPE_SID = 2, PIDTYPE_MAX = 3 } ; 197 struct pid_namespace ; 197 struct upid { int nr; struct pid_namespace *ns; struct hlist_node pid_chain; } ; 56 struct pid { atomic_t count; unsigned int level; struct hlist_head tasks[3U]; struct callback_head rcu; struct upid numbers[1U]; } ; 68 struct pid_link { struct hlist_node node; struct pid *pid; } ; 22 struct kernel_cap_struct { __u32 cap[2U]; } ; 25 typedef struct kernel_cap_struct kernel_cap_t; 217 struct fiemap_extent { __u64 fe_logical; __u64 fe_physical; __u64 fe_length; __u64 fe_reserved64[2U]; __u32 fe_flags; __u32 fe_reserved[3U]; } ; 38 enum migrate_mode { MIGRATE_ASYNC = 0, MIGRATE_SYNC_LIGHT = 1, MIGRATE_SYNC = 2 } ; 44 struct rcuwait { struct task_struct *task; } ; 32 enum rcu_sync_type { RCU_SYNC = 0, RCU_SCHED_SYNC = 1, RCU_BH_SYNC = 2 } ; 38 struct rcu_sync { int gp_state; int gp_count; wait_queue_head_t gp_wait; int cb_state; struct callback_head cb_head; enum rcu_sync_type gp_type; } ; 66 struct percpu_rw_semaphore { struct rcu_sync rss; unsigned int *read_count; struct rw_semaphore rw_sem; struct rcuwait writer; int readers_block; } ; 144 struct delayed_call { void (*fn)(void *); void *arg; } ; 25 struct __anonstruct_uuid_t_308 { __u8 b[16U]; } ; 25 typedef struct __anonstruct_uuid_t_308 uuid_t; 6 typedef u32 errseq_t; 302 struct backing_dev_info ; 303 struct bdi_writeback ; 305 struct export_operations ; 308 struct kiocb ; 309 struct pipe_inode_info ; 310 struct poll_table_struct ; 311 struct kstatfs ; 312 struct swap_info_struct ; 313 struct iov_iter ; 314 struct fscrypt_info ; 315 struct fscrypt_operations ; 79 struct iattr { unsigned int ia_valid; umode_t ia_mode; kuid_t ia_uid; kgid_t ia_gid; loff_t ia_size; struct timespec ia_atime; struct timespec ia_mtime; struct timespec ia_ctime; struct file *ia_file; } ; 213 struct dquot ; 214 struct kqid ; 19 typedef __kernel_uid32_t projid_t; 23 struct __anonstruct_kprojid_t_309 { projid_t val; } ; 23 typedef struct __anonstruct_kprojid_t_309 kprojid_t; 181 enum quota_type { USRQUOTA = 0, GRPQUOTA = 1, PRJQUOTA = 2 } ; 66 typedef long long qsize_t; 67 union __anonunion____missing_field_name_310 { kuid_t uid; kgid_t gid; kprojid_t projid; } ; 67 struct kqid { union __anonunion____missing_field_name_310 __annonCompField58; enum quota_type type; } ; 194 struct mem_dqblk { qsize_t dqb_bhardlimit; qsize_t dqb_bsoftlimit; qsize_t dqb_curspace; qsize_t dqb_rsvspace; qsize_t dqb_ihardlimit; qsize_t dqb_isoftlimit; qsize_t dqb_curinodes; time64_t dqb_btime; time64_t dqb_itime; } ; 216 struct quota_format_type ; 217 struct mem_dqinfo { struct quota_format_type *dqi_format; int dqi_fmt_id; struct list_head dqi_dirty_list; unsigned long dqi_flags; unsigned int dqi_bgrace; unsigned int dqi_igrace; qsize_t dqi_max_spc_limit; qsize_t dqi_max_ino_limit; void *dqi_priv; } ; 282 struct dquot { struct hlist_node dq_hash; struct list_head dq_inuse; struct list_head dq_free; struct list_head dq_dirty; struct mutex dq_lock; atomic_t dq_count; wait_queue_head_t dq_wait_unused; struct super_block *dq_sb; struct kqid dq_id; loff_t dq_off; unsigned long dq_flags; struct mem_dqblk dq_dqb; } ; 309 struct quota_format_ops { int (*check_quota_file)(struct super_block *, int); int (*read_file_info)(struct super_block *, int); int (*write_file_info)(struct super_block *, int); int (*free_file_info)(struct super_block *, int); int (*read_dqblk)(struct dquot *); int (*commit_dqblk)(struct dquot *); int (*release_dqblk)(struct dquot *); int (*get_next_id)(struct super_block *, struct kqid *); } ; 321 struct dquot_operations { int (*write_dquot)(struct dquot *); struct dquot * (*alloc_dquot)(struct super_block *, int); void (*destroy_dquot)(struct dquot *); int (*acquire_dquot)(struct dquot *); int (*release_dquot)(struct dquot *); int (*mark_dirty)(struct dquot *); int (*write_info)(struct super_block *, int); qsize_t * (*get_reserved_space)(struct inode *); int (*get_projid)(struct inode *, kprojid_t *); int (*get_inode_usage)(struct inode *, qsize_t *); int (*get_next_id)(struct super_block *, struct kqid *); } ; 340 struct qc_dqblk { int d_fieldmask; u64 d_spc_hardlimit; u64 d_spc_softlimit; u64 d_ino_hardlimit; u64 d_ino_softlimit; u64 d_space; u64 d_ino_count; s64 d_ino_timer; s64 d_spc_timer; int d_ino_warns; int d_spc_warns; u64 d_rt_spc_hardlimit; u64 d_rt_spc_softlimit; u64 d_rt_space; s64 d_rt_spc_timer; int d_rt_spc_warns; } ; 363 struct qc_type_state { unsigned int flags; unsigned int spc_timelimit; unsigned int ino_timelimit; unsigned int rt_spc_timelimit; unsigned int spc_warnlimit; unsigned int ino_warnlimit; unsigned int rt_spc_warnlimit; unsigned long long ino; blkcnt_t blocks; blkcnt_t nextents; } ; 409 struct qc_state { unsigned int s_incoredqs; struct qc_type_state s_state[3U]; } ; 420 struct qc_info { int i_fieldmask; unsigned int i_flags; unsigned int i_spc_timelimit; unsigned int i_ino_timelimit; unsigned int i_rt_spc_timelimit; unsigned int i_spc_warnlimit; unsigned int i_ino_warnlimit; unsigned int i_rt_spc_warnlimit; } ; 433 struct quotactl_ops { int (*quota_on)(struct super_block *, int, int, const struct path *); int (*quota_off)(struct super_block *, int); int (*quota_enable)(struct super_block *, unsigned int); int (*quota_disable)(struct super_block *, unsigned int); int (*quota_sync)(struct super_block *, int); int (*set_info)(struct super_block *, int, struct qc_info *); int (*get_dqblk)(struct super_block *, struct kqid , struct qc_dqblk *); int (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *); int (*set_dqblk)(struct super_block *, struct kqid , struct qc_dqblk *); int (*get_state)(struct super_block *, struct qc_state *); int (*rm_xquota)(struct super_block *, unsigned int); } ; 449 struct quota_format_type { int qf_fmt_id; const struct quota_format_ops *qf_ops; struct module *qf_owner; struct quota_format_type *qf_next; } ; 513 struct quota_info { unsigned int flags; struct mutex dqio_mutex; struct inode *files[3U]; struct mem_dqinfo info[3U]; const struct quota_format_ops *ops[3U]; } ; 542 struct writeback_control ; 543 enum rw_hint { WRITE_LIFE_NOT_SET = 0, WRITE_LIFE_NONE = 1, WRITE_LIFE_SHORT = 2, WRITE_LIFE_MEDIUM = 3, WRITE_LIFE_LONG = 4, WRITE_LIFE_EXTREME = 5 } ; 552 struct kiocb { struct file *ki_filp; loff_t ki_pos; void (*ki_complete)(struct kiocb *, long, long); void *private; int ki_flags; enum rw_hint ki_hint; } ; 326 struct address_space_operations { int (*writepage)(struct page *, struct writeback_control *); int (*readpage)(struct file *, struct page *); int (*writepages)(struct address_space *, struct writeback_control *); int (*set_page_dirty)(struct page *); int (*readpages)(struct file *, struct address_space *, struct list_head *, unsigned int); int (*write_begin)(struct file *, struct address_space *, loff_t , unsigned int, unsigned int, struct page **, void **); int (*write_end)(struct file *, struct address_space *, loff_t , unsigned int, unsigned int, struct page *, void *); sector_t (*bmap)(struct address_space *, sector_t ); void (*invalidatepage)(struct page *, unsigned int, unsigned int); int (*releasepage)(struct page *, gfp_t ); void (*freepage)(struct page *); ssize_t (*direct_IO)(struct kiocb *, struct iov_iter *); int (*migratepage)(struct address_space *, struct page *, struct page *, enum migrate_mode ); bool (*isolate_page)(struct page *, isolate_mode_t ); void (*putback_page)(struct page *); int (*launder_page)(struct page *); int (*is_partially_uptodate)(struct page *, unsigned long, unsigned long); void (*is_dirty_writeback)(struct page *, bool *, bool *); int (*error_remove_page)(struct address_space *, struct page *); int (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *); void (*swap_deactivate)(struct file *); } ; 385 struct address_space { struct inode *host; struct radix_tree_root page_tree; spinlock_t tree_lock; atomic_t i_mmap_writable; struct rb_root i_mmap; struct rw_semaphore i_mmap_rwsem; unsigned long nrpages; unsigned long nrexceptional; unsigned long writeback_index; const struct address_space_operations *a_ops; unsigned long flags; spinlock_t private_lock; gfp_t gfp_mask; struct list_head private_list; void *private_data; errseq_t wb_err; } ; 408 struct request_queue ; 409 struct hd_struct ; 409 struct gendisk ; 409 struct block_device { dev_t bd_dev; int bd_openers; struct inode *bd_inode; struct super_block *bd_super; struct mutex bd_mutex; void *bd_claiming; void *bd_holder; int bd_holders; bool bd_write_holder; struct list_head bd_holder_disks; struct block_device *bd_contains; unsigned int bd_block_size; struct hd_struct *bd_part; unsigned int bd_part_count; int bd_invalidated; struct gendisk *bd_disk; struct request_queue *bd_queue; struct backing_dev_info *bd_bdi; struct list_head bd_list; unsigned long bd_private; int bd_fsfreeze_count; struct mutex bd_fsfreeze_mutex; } ; 525 struct posix_acl ; 552 struct fsnotify_mark_connector ; 553 struct inode_operations ; 553 union __anonunion____missing_field_name_315 { const unsigned int i_nlink; unsigned int __i_nlink; } ; 553 union __anonunion____missing_field_name_316 { struct hlist_head i_dentry; struct callback_head i_rcu; } ; 553 struct file_lock_context ; 553 struct cdev ; 553 union __anonunion____missing_field_name_317 { struct pipe_inode_info *i_pipe; struct block_device *i_bdev; struct cdev *i_cdev; char *i_link; unsigned int i_dir_seq; } ; 553 struct inode { umode_t i_mode; unsigned short i_opflags; kuid_t i_uid; kgid_t i_gid; unsigned int i_flags; struct posix_acl *i_acl; struct posix_acl *i_default_acl; const struct inode_operations *i_op; struct super_block *i_sb; struct address_space *i_mapping; void *i_security; unsigned long i_ino; union __anonunion____missing_field_name_315 __annonCompField59; dev_t i_rdev; loff_t i_size; struct timespec i_atime; struct timespec i_mtime; struct timespec i_ctime; spinlock_t i_lock; unsigned short i_bytes; unsigned int i_blkbits; enum rw_hint i_write_hint; blkcnt_t i_blocks; unsigned long i_state; struct rw_semaphore i_rwsem; unsigned long dirtied_when; unsigned long dirtied_time_when; struct hlist_node i_hash; struct list_head i_io_list; struct bdi_writeback *i_wb; int i_wb_frn_winner; u16 i_wb_frn_avg_time; u16 i_wb_frn_history; struct list_head i_lru; struct list_head i_sb_list; struct list_head i_wb_list; union __anonunion____missing_field_name_316 __annonCompField60; u64 i_version; atomic_t i_count; atomic_t i_dio_count; atomic_t i_writecount; atomic_t i_readcount; const struct file_operations *i_fop; struct file_lock_context *i_flctx; struct address_space i_data; struct list_head i_devices; union __anonunion____missing_field_name_317 __annonCompField61; __u32 i_generation; __u32 i_fsnotify_mask; struct fsnotify_mark_connector *i_fsnotify_marks; struct fscrypt_info *i_crypt_info; void *i_private; } ; 816 struct fown_struct { rwlock_t lock; struct pid *pid; enum pid_type pid_type; kuid_t uid; kuid_t euid; int signum; } ; 824 struct file_ra_state { unsigned long start; unsigned int size; unsigned int async_size; unsigned int ra_pages; unsigned int mmap_miss; loff_t prev_pos; } ; 847 union __anonunion_f_u_318 { struct llist_node fu_llist; struct callback_head fu_rcuhead; } ; 847 struct file { union __anonunion_f_u_318 f_u; struct path f_path; struct inode *f_inode; const struct file_operations *f_op; spinlock_t f_lock; enum rw_hint f_write_hint; atomic_long_t f_count; unsigned int f_flags; fmode_t f_mode; struct mutex f_pos_lock; loff_t f_pos; struct fown_struct f_owner; const struct cred *f_cred; struct file_ra_state f_ra; u64 f_version; void *f_security; void *private_data; struct list_head f_ep_links; struct list_head f_tfile_llink; struct address_space *f_mapping; errseq_t f_wb_err; } ; 936 typedef void *fl_owner_t; 937 struct file_lock ; 938 struct file_lock_operations { void (*fl_copy_lock)(struct file_lock *, struct file_lock *); void (*fl_release_private)(struct file_lock *); } ; 944 struct lock_manager_operations { int (*lm_compare_owner)(struct file_lock *, struct file_lock *); unsigned long int (*lm_owner_key)(struct file_lock *); fl_owner_t (*lm_get_owner)(fl_owner_t ); void (*lm_put_owner)(fl_owner_t ); void (*lm_notify)(struct file_lock *); int (*lm_grant)(struct file_lock *, int); bool (*lm_break)(struct file_lock *); int (*lm_change)(struct file_lock *, int, struct list_head *); void (*lm_setup)(struct file_lock *, void **); } ; 971 struct nlm_lockowner ; 972 struct nfs_lock_info { u32 state; struct nlm_lockowner *owner; struct list_head list; } ; 14 struct nfs4_lock_state ; 15 struct nfs4_lock_info { struct nfs4_lock_state *owner; } ; 19 struct fasync_struct ; 19 struct __anonstruct_afs_320 { struct list_head link; int state; } ; 19 union __anonunion_fl_u_319 { struct nfs_lock_info nfs_fl; struct nfs4_lock_info nfs4_fl; struct __anonstruct_afs_320 afs; } ; 19 struct file_lock { struct file_lock *fl_next; struct list_head fl_list; struct hlist_node fl_link; struct list_head fl_block; fl_owner_t fl_owner; unsigned int fl_flags; unsigned char fl_type; unsigned int fl_pid; int fl_link_cpu; struct pid *fl_nspid; wait_queue_head_t fl_wait; struct file *fl_file; loff_t fl_start; loff_t fl_end; struct fasync_struct *fl_fasync; unsigned long fl_break_time; unsigned long fl_downgrade_time; const struct file_lock_operations *fl_ops; const struct lock_manager_operations *fl_lmops; union __anonunion_fl_u_319 fl_u; } ; 1024 struct file_lock_context { spinlock_t flc_lock; struct list_head flc_flock; struct list_head flc_posix; struct list_head flc_lease; } ; 1089 struct files_struct ; 1242 struct fasync_struct { spinlock_t fa_lock; int magic; int fa_fd; struct fasync_struct *fa_next; struct file *fa_file; struct callback_head fa_rcu; } ; 1277 struct sb_writers { int frozen; wait_queue_head_t wait_unfrozen; struct percpu_rw_semaphore rw_sem[3U]; } ; 1307 struct super_operations ; 1307 struct xattr_handler ; 1307 struct mtd_info ; 1307 struct super_block { struct list_head s_list; dev_t s_dev; unsigned char s_blocksize_bits; unsigned long s_blocksize; loff_t s_maxbytes; struct file_system_type *s_type; const struct super_operations *s_op; const struct dquot_operations *dq_op; const struct quotactl_ops *s_qcop; const struct export_operations *s_export_op; unsigned long s_flags; unsigned long s_iflags; unsigned long s_magic; struct dentry *s_root; struct rw_semaphore s_umount; int s_count; atomic_t s_active; void *s_security; const struct xattr_handler **s_xattr; const struct fscrypt_operations *s_cop; struct hlist_bl_head s_anon; struct list_head s_mounts; struct block_device *s_bdev; struct backing_dev_info *s_bdi; struct mtd_info *s_mtd; struct hlist_node s_instances; unsigned int s_quota_types; struct quota_info s_dquot; struct sb_writers s_writers; char s_id[32U]; uuid_t s_uuid; void *s_fs_info; unsigned int s_max_links; fmode_t s_mode; u32 s_time_gran; struct mutex s_vfs_rename_mutex; char *s_subtype; const struct dentry_operations *s_d_op; int cleancache_poolid; struct shrinker s_shrink; atomic_long_t s_remove_count; int s_readonly_remount; struct workqueue_struct *s_dio_done_wq; struct hlist_head s_pins; struct user_namespace *s_user_ns; struct list_lru s_dentry_lru; struct list_lru s_inode_lru; struct callback_head rcu; struct work_struct destroy_work; struct mutex s_sync_lock; int s_stack_depth; spinlock_t s_inode_list_lock; struct list_head s_inodes; spinlock_t s_inode_wblist_lock; struct list_head s_inodes_wb; } ; 1588 struct fiemap_extent_info { unsigned int fi_flags; unsigned int fi_extents_mapped; unsigned int fi_extents_max; struct fiemap_extent *fi_extents_start; } ; 1601 struct dir_context ; 1626 struct dir_context { int (*actor)(struct dir_context *, const char *, int, loff_t , u64 , unsigned int); loff_t pos; } ; 1633 struct file_operations { struct module *owner; loff_t (*llseek)(struct file *, loff_t , int); ssize_t (*read)(struct file *, char *, size_t , loff_t *); ssize_t (*write)(struct file *, const char *, size_t , loff_t *); ssize_t (*read_iter)(struct kiocb *, struct iov_iter *); ssize_t (*write_iter)(struct kiocb *, struct iov_iter *); int (*iterate)(struct file *, struct dir_context *); int (*iterate_shared)(struct file *, struct dir_context *); unsigned int (*poll)(struct file *, struct poll_table_struct *); long int (*unlocked_ioctl)(struct file *, unsigned int, unsigned long); long int (*compat_ioctl)(struct file *, unsigned int, unsigned long); int (*mmap)(struct file *, struct vm_area_struct *); int (*open)(struct inode *, struct file *); int (*flush)(struct file *, fl_owner_t ); int (*release)(struct inode *, struct file *); int (*fsync)(struct file *, loff_t , loff_t , int); int (*fasync)(int, struct file *, int); int (*lock)(struct file *, int, struct file_lock *); ssize_t (*sendpage)(struct file *, struct page *, int, size_t , loff_t *, int); unsigned long int (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); int (*check_flags)(int); int (*flock)(struct file *, int, struct file_lock *); ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t , unsigned int); ssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t , unsigned int); int (*setlease)(struct file *, long, struct file_lock **, void **); long int (*fallocate)(struct file *, int, loff_t , loff_t ); void (*show_fdinfo)(struct seq_file *, struct file *); ssize_t (*copy_file_range)(struct file *, loff_t , struct file *, loff_t , size_t , unsigned int); int (*clone_file_range)(struct file *, loff_t , struct file *, loff_t , u64 ); ssize_t (*dedupe_file_range)(struct file *, u64 , u64 , struct file *, u64 ); } ; 1701 struct inode_operations { struct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int); const char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *); int (*permission)(struct inode *, int); struct posix_acl * (*get_acl)(struct inode *, int); int (*readlink)(struct dentry *, char *, int); int (*create)(struct inode *, struct dentry *, umode_t , bool ); int (*link)(struct dentry *, struct inode *, struct dentry *); int (*unlink)(struct inode *, struct dentry *); int (*symlink)(struct inode *, struct dentry *, const char *); int (*mkdir)(struct inode *, struct dentry *, umode_t ); int (*rmdir)(struct inode *, struct dentry *); int (*mknod)(struct inode *, struct dentry *, umode_t , dev_t ); int (*rename)(struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*setattr)(struct dentry *, struct iattr *); int (*getattr)(const struct path *, struct kstat *, u32 , unsigned int); ssize_t (*listxattr)(struct dentry *, char *, size_t ); int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 , u64 ); int (*update_time)(struct inode *, struct timespec *, int); int (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t , int *); int (*tmpfile)(struct inode *, struct dentry *, umode_t ); int (*set_acl)(struct inode *, struct posix_acl *, int); } ; 1774 struct super_operations { struct inode * (*alloc_inode)(struct super_block *); void (*destroy_inode)(struct inode *); void (*dirty_inode)(struct inode *, int); int (*write_inode)(struct inode *, struct writeback_control *); int (*drop_inode)(struct inode *); void (*evict_inode)(struct inode *); void (*put_super)(struct super_block *); int (*sync_fs)(struct super_block *, int); int (*freeze_super)(struct super_block *); int (*freeze_fs)(struct super_block *); int (*thaw_super)(struct super_block *); int (*unfreeze_fs)(struct super_block *); int (*statfs)(struct dentry *, struct kstatfs *); int (*remount_fs)(struct super_block *, int *, char *); void (*umount_begin)(struct super_block *); int (*show_options)(struct seq_file *, struct dentry *); int (*show_devname)(struct seq_file *, struct dentry *); int (*show_path)(struct seq_file *, struct dentry *); int (*show_stats)(struct seq_file *, struct dentry *); ssize_t (*quota_read)(struct super_block *, int, char *, size_t , loff_t ); ssize_t (*quota_write)(struct super_block *, int, const char *, size_t , loff_t ); struct dquot ** (*get_dquots)(struct inode *); int (*bdev_try_to_free_page)(struct super_block *, struct page *, gfp_t ); long int (*nr_cached_objects)(struct super_block *, struct shrink_control *); long int (*free_cached_objects)(struct super_block *, struct shrink_control *); } ; 2040 struct file_system_type { const char *name; int fs_flags; struct dentry * (*mount)(struct file_system_type *, int, const char *, void *); void (*kill_sb)(struct super_block *); struct module *owner; struct file_system_type *next; struct hlist_head fs_supers; struct lock_class_key s_lock_key; struct lock_class_key s_umount_key; struct lock_class_key s_vfs_rename_key; struct lock_class_key s_writers_key[3U]; struct lock_class_key i_lock_key; struct lock_class_key i_mutex_key; struct lock_class_key i_mutex_dir_key; } ; 3331 struct assoc_array_ptr ; 3331 struct assoc_array { struct assoc_array_ptr *root; unsigned long nr_leaves_on_tree; } ; 32 typedef int32_t key_serial_t; 35 typedef uint32_t key_perm_t; 36 struct key ; 37 struct user_struct ; 38 struct signal_struct ; 39 struct key_type ; 43 struct keyring_index_key { struct key_type *type; const char *description; size_t desc_len; } ; 92 union key_payload { void *rcu_data0; void *data[4U]; } ; 131 struct key_restriction { int (*check)(struct key *, const struct key_type *, const union key_payload *, struct key *); struct key *key; struct key_type *keytype; } ; 140 union __anonunion____missing_field_name_321 { struct list_head graveyard_link; struct rb_node serial_node; } ; 140 struct key_user ; 140 union __anonunion____missing_field_name_322 { time_t expiry; time_t revoked_at; } ; 140 struct __anonstruct____missing_field_name_324 { struct key_type *type; char *description; } ; 140 union __anonunion____missing_field_name_323 { struct keyring_index_key index_key; struct __anonstruct____missing_field_name_324 __annonCompField64; } ; 140 struct __anonstruct____missing_field_name_326 { struct list_head name_link; struct assoc_array keys; } ; 140 union __anonunion____missing_field_name_325 { union key_payload payload; struct __anonstruct____missing_field_name_326 __annonCompField66; int reject_error; } ; 140 struct key { refcount_t usage; key_serial_t serial; union __anonunion____missing_field_name_321 __annonCompField62; struct rw_semaphore sem; struct key_user *user; void *security; union __anonunion____missing_field_name_322 __annonCompField63; time_t last_used_at; kuid_t uid; kgid_t gid; key_perm_t perm; unsigned short quotalen; unsigned short datalen; unsigned long flags; union __anonunion____missing_field_name_323 __annonCompField65; union __anonunion____missing_field_name_325 __annonCompField67; struct key_restriction *restrict_link; } ; 390 struct audit_context ; 45 struct sem_undo_list ; 45 struct sysv_sem { struct sem_undo_list *undo_list; } ; 26 struct sysv_shm { struct list_head shm_clist; } ; 12 enum kcov_mode { KCOV_MODE_DISABLED = 0, KCOV_MODE_TRACE = 1 } ; 84 struct plist_node { int prio; struct list_head prio_list; struct list_head node_list; } ; 299 struct timerqueue_node { struct rb_node node; ktime_t expires; } ; 12 struct timerqueue_head { struct rb_root head; struct timerqueue_node *next; } ; 50 struct hrtimer_clock_base ; 51 struct hrtimer_cpu_base ; 60 enum hrtimer_restart { HRTIMER_NORESTART = 0, HRTIMER_RESTART = 1 } ; 65 struct hrtimer { struct timerqueue_node node; ktime_t _softexpires; enum hrtimer_restart (*function)(struct hrtimer *); struct hrtimer_clock_base *base; u8 state; u8 is_rel; } ; 113 struct hrtimer_clock_base { struct hrtimer_cpu_base *cpu_base; int index; clockid_t clockid; struct timerqueue_head active; ktime_t (*get_time)(); ktime_t offset; } ; 146 struct hrtimer_cpu_base { raw_spinlock_t lock; seqcount_t seq; struct hrtimer *running; unsigned int cpu; unsigned int active_bases; unsigned int clock_was_set_seq; bool migration_enabled; bool nohz_active; unsigned char in_hrtirq; unsigned char hres_active; unsigned char hang_detected; ktime_t expires_next; struct hrtimer *next_timer; unsigned int nr_events; unsigned int nr_retries; unsigned int nr_hangs; unsigned int max_hang_time; struct hrtimer_clock_base clock_base[4U]; } ; 43 struct seccomp_filter ; 44 struct seccomp { int mode; struct seccomp_filter *filter; } ; 11 struct latency_record { unsigned long backtrace[12U]; unsigned int count; unsigned long time; unsigned long max; } ; 24 struct __anonstruct_sigset_t_327 { unsigned long sig[1U]; } ; 24 typedef struct __anonstruct_sigset_t_327 sigset_t; 25 struct siginfo ; 38 union sigval { int sival_int; void *sival_ptr; } ; 10 typedef union sigval sigval_t; 11 struct __anonstruct__kill_329 { __kernel_pid_t _pid; __kernel_uid32_t _uid; } ; 11 struct __anonstruct__timer_330 { __kernel_timer_t _tid; int _overrun; char _pad[0U]; sigval_t _sigval; int _sys_private; } ; 11 struct __anonstruct__rt_331 { __kernel_pid_t _pid; __kernel_uid32_t _uid; sigval_t _sigval; } ; 11 struct __anonstruct__sigchld_332 { __kernel_pid_t _pid; __kernel_uid32_t _uid; int _status; __kernel_clock_t _utime; __kernel_clock_t _stime; } ; 11 struct __anonstruct__addr_bnd_335 { void *_lower; void *_upper; } ; 11 union __anonunion____missing_field_name_334 { struct __anonstruct__addr_bnd_335 _addr_bnd; __u32 _pkey; } ; 11 struct __anonstruct__sigfault_333 { void *_addr; short _addr_lsb; union __anonunion____missing_field_name_334 __annonCompField68; } ; 11 struct __anonstruct__sigpoll_336 { long _band; int _fd; } ; 11 struct __anonstruct__sigsys_337 { void *_call_addr; int _syscall; unsigned int _arch; } ; 11 union __anonunion__sifields_328 { int _pad[28U]; struct __anonstruct__kill_329 _kill; struct __anonstruct__timer_330 _timer; struct __anonstruct__rt_331 _rt; struct __anonstruct__sigchld_332 _sigchld; struct __anonstruct__sigfault_333 _sigfault; struct __anonstruct__sigpoll_336 _sigpoll; struct __anonstruct__sigsys_337 _sigsys; } ; 11 struct siginfo { int si_signo; int si_errno; int si_code; union __anonunion__sifields_328 _sifields; } ; 118 typedef struct siginfo siginfo_t; 21 struct sigpending { struct list_head list; sigset_t signal; } ; 65 struct task_io_accounting { u64 rchar; u64 wchar; u64 syscr; u64 syscw; u64 read_bytes; u64 write_bytes; u64 cancelled_write_bytes; } ; 45 struct bio_list ; 46 struct blk_plug ; 47 struct cfs_rq ; 48 struct fs_struct ; 49 struct futex_pi_state ; 50 struct io_context ; 51 struct nameidata ; 52 struct perf_event_context ; 54 struct reclaim_state ; 55 struct robust_list_head ; 58 struct sighand_struct ; 59 struct task_delay_info ; 60 struct task_group ; 187 struct prev_cputime { u64 utime; u64 stime; raw_spinlock_t lock; } ; 203 struct task_cputime { u64 utime; u64 stime; unsigned long long sum_exec_runtime; } ; 243 struct sched_info { unsigned long pcount; unsigned long long run_delay; unsigned long long last_arrival; unsigned long long last_queued; } ; 262 struct load_weight { unsigned long weight; u32 inv_weight; } ; 279 struct sched_avg { u64 last_update_time; u64 load_sum; u32 util_sum; u32 period_contrib; unsigned long load_avg; unsigned long util_avg; } ; 340 struct sched_statistics { u64 wait_start; u64 wait_max; u64 wait_count; u64 wait_sum; u64 iowait_count; u64 iowait_sum; u64 sleep_start; u64 sleep_max; s64 sum_sleep_runtime; u64 block_start; u64 block_max; u64 exec_max; u64 slice_max; u64 nr_migrations_cold; u64 nr_failed_migrations_affine; u64 nr_failed_migrations_running; u64 nr_failed_migrations_hot; u64 nr_forced_migrations; u64 nr_wakeups; u64 nr_wakeups_sync; u64 nr_wakeups_migrate; u64 nr_wakeups_local; u64 nr_wakeups_remote; u64 nr_wakeups_affine; u64 nr_wakeups_affine_attempts; u64 nr_wakeups_passive; u64 nr_wakeups_idle; } ; 375 struct sched_entity { struct load_weight load; struct rb_node run_node; struct list_head group_node; unsigned int on_rq; u64 exec_start; u64 sum_exec_runtime; u64 vruntime; u64 prev_sum_exec_runtime; u64 nr_migrations; struct sched_statistics statistics; int depth; struct sched_entity *parent; struct cfs_rq *cfs_rq; struct cfs_rq *my_q; struct sched_avg avg; } ; 411 struct rt_rq ; 411 struct sched_rt_entity { struct list_head run_list; unsigned long timeout; unsigned long watchdog_stamp; unsigned int time_slice; unsigned short on_rq; unsigned short on_list; struct sched_rt_entity *back; struct sched_rt_entity *parent; struct rt_rq *rt_rq; struct rt_rq *my_q; } ; 429 struct sched_dl_entity { struct rb_node rb_node; u64 dl_runtime; u64 dl_deadline; u64 dl_period; u64 dl_bw; u64 dl_density; s64 runtime; u64 deadline; unsigned int flags; int dl_throttled; int dl_boosted; int dl_yielded; int dl_non_contending; struct hrtimer dl_timer; struct hrtimer inactive_timer; } ; 514 struct wake_q_node { struct wake_q_node *next; } ; 518 struct sched_class ; 518 struct rt_mutex_waiter ; 518 struct css_set ; 518 struct compat_robust_list_head ; 518 struct numa_group ; 518 struct kcov ; 518 struct task_struct { struct thread_info thread_info; volatile long state; void *stack; atomic_t usage; unsigned int flags; unsigned int ptrace; struct llist_node wake_entry; int on_cpu; unsigned int cpu; unsigned int wakee_flips; unsigned long wakee_flip_decay_ts; struct task_struct *last_wakee; int wake_cpu; int on_rq; int prio; int static_prio; int normal_prio; unsigned int rt_priority; const struct sched_class *sched_class; struct sched_entity se; struct sched_rt_entity rt; struct task_group *sched_task_group; struct sched_dl_entity dl; struct hlist_head preempt_notifiers; unsigned int policy; int nr_cpus_allowed; cpumask_t cpus_allowed; unsigned long rcu_tasks_nvcsw; bool rcu_tasks_holdout; struct list_head rcu_tasks_holdout_list; int rcu_tasks_idle_cpu; struct sched_info sched_info; struct list_head tasks; struct plist_node pushable_tasks; struct rb_node pushable_dl_tasks; struct mm_struct *mm; struct mm_struct *active_mm; struct vmacache vmacache; struct task_rss_stat rss_stat; int exit_state; int exit_code; int exit_signal; int pdeath_signal; unsigned long jobctl; unsigned int personality; unsigned char sched_reset_on_fork; unsigned char sched_contributes_to_load; unsigned char sched_migrated; unsigned char sched_remote_wakeup; unsigned char; unsigned char in_execve; unsigned char in_iowait; unsigned char restore_sigmask; unsigned char memcg_may_oom; unsigned char memcg_kmem_skip_account; unsigned char brk_randomized; unsigned char no_cgroup_migration; unsigned long atomic_flags; struct restart_block restart_block; pid_t pid; pid_t tgid; struct task_struct *real_parent; struct task_struct *parent; struct list_head children; struct list_head sibling; struct task_struct *group_leader; struct list_head ptraced; struct list_head ptrace_entry; struct pid_link pids[3U]; struct list_head thread_group; struct list_head thread_node; struct completion *vfork_done; int *set_child_tid; int *clear_child_tid; u64 utime; u64 stime; u64 gtime; struct prev_cputime prev_cputime; unsigned long nvcsw; unsigned long nivcsw; u64 start_time; u64 real_start_time; unsigned long min_flt; unsigned long maj_flt; struct task_cputime cputime_expires; struct list_head cpu_timers[3U]; const struct cred *ptracer_cred; const struct cred *real_cred; const struct cred *cred; char comm[16U]; struct nameidata *nameidata; struct sysv_sem sysvsem; struct sysv_shm sysvshm; unsigned long last_switch_count; struct fs_struct *fs; struct files_struct *files; struct nsproxy *nsproxy; struct signal_struct *signal; struct sighand_struct *sighand; sigset_t blocked; sigset_t real_blocked; sigset_t saved_sigmask; struct sigpending pending; unsigned long sas_ss_sp; size_t sas_ss_size; unsigned int sas_ss_flags; struct callback_head *task_works; struct audit_context *audit_context; kuid_t loginuid; unsigned int sessionid; struct seccomp seccomp; u32 parent_exec_id; u32 self_exec_id; spinlock_t alloc_lock; raw_spinlock_t pi_lock; struct wake_q_node wake_q; struct rb_root pi_waiters; struct rb_node *pi_waiters_leftmost; struct task_struct *pi_top_task; struct rt_mutex_waiter *pi_blocked_on; struct mutex_waiter *blocked_on; unsigned int irq_events; unsigned long hardirq_enable_ip; unsigned long hardirq_disable_ip; unsigned int hardirq_enable_event; unsigned int hardirq_disable_event; int hardirqs_enabled; int hardirq_context; unsigned long softirq_disable_ip; unsigned long softirq_enable_ip; unsigned int softirq_disable_event; unsigned int softirq_enable_event; int softirqs_enabled; int softirq_context; u64 curr_chain_key; int lockdep_depth; unsigned int lockdep_recursion; struct held_lock held_locks[48U]; gfp_t lockdep_reclaim_gfp; unsigned int in_ubsan; void *journal_info; struct bio_list *bio_list; struct blk_plug *plug; struct reclaim_state *reclaim_state; struct backing_dev_info *backing_dev_info; struct io_context *io_context; unsigned long ptrace_message; siginfo_t *last_siginfo; struct task_io_accounting ioac; u64 acct_rss_mem1; u64 acct_vm_mem1; u64 acct_timexpd; nodemask_t mems_allowed; seqcount_t mems_allowed_seq; int cpuset_mem_spread_rotor; int cpuset_slab_spread_rotor; struct css_set *cgroups; struct list_head cg_list; int closid; struct robust_list_head *robust_list; struct compat_robust_list_head *compat_robust_list; struct list_head pi_state_list; struct futex_pi_state *pi_state_cache; struct perf_event_context *perf_event_ctxp[2U]; struct mutex perf_event_mutex; struct list_head perf_event_list; struct mempolicy *mempolicy; short il_prev; short pref_node_fork; int numa_scan_seq; unsigned int numa_scan_period; unsigned int numa_scan_period_max; int numa_preferred_nid; unsigned long numa_migrate_retry; u64 node_stamp; u64 last_task_numa_placement; u64 last_sum_exec_runtime; struct callback_head numa_work; struct list_head numa_entry; struct numa_group *numa_group; unsigned long *numa_faults; unsigned long total_numa_faults; unsigned long numa_faults_locality[3U]; unsigned long numa_pages_migrated; struct tlbflush_unmap_batch tlb_ubc; struct callback_head rcu; struct pipe_inode_info *splice_pipe; struct page_frag task_frag; struct task_delay_info *delays; int make_it_fail; unsigned int fail_nth; int nr_dirtied; int nr_dirtied_pause; unsigned long dirty_paused_when; int latency_record_count; struct latency_record latency_record[32U]; u64 timer_slack_ns; u64 default_timer_slack_ns; unsigned int kasan_depth; unsigned long trace; unsigned long trace_recursion; enum kcov_mode kcov_mode; unsigned int kcov_size; void *kcov_area; struct kcov *kcov; struct mem_cgroup *memcg_in_oom; gfp_t memcg_oom_gfp_mask; int memcg_oom_order; unsigned int memcg_nr_pages_over_high; struct uprobe_task *utask; unsigned int sequential_io; unsigned int sequential_io_avg; unsigned long task_state_change; int pagefault_disabled; struct task_struct *oom_reaper_list; atomic_t stack_refcount; int patch_state; void *security; struct thread_struct thread; } ; 1607 struct user_struct { atomic_t __count; atomic_t processes; atomic_t sigpending; atomic_t fanotify_listeners; atomic_long_t epoll_watches; unsigned long mq_bytes; unsigned long locked_shm; unsigned long unix_inflight; atomic_long_t pipe_bufs; struct key *uid_keyring; struct key *session_keyring; struct hlist_node uidhash_node; kuid_t uid; atomic_long_t locked_vm; } ; 60 struct group_info { atomic_t usage; int ngroups; kgid_t gid[0U]; } ; 86 struct cred { atomic_t usage; atomic_t subscribers; void *put_addr; unsigned int magic; kuid_t uid; kgid_t gid; kuid_t suid; kgid_t sgid; kuid_t euid; kgid_t egid; kuid_t fsuid; kgid_t fsgid; unsigned int securebits; kernel_cap_t cap_inheritable; kernel_cap_t cap_permitted; kernel_cap_t cap_effective; kernel_cap_t cap_bset; kernel_cap_t cap_ambient; unsigned char jit_keyring; struct key *session_keyring; struct key *process_keyring; struct key *thread_keyring; struct key *request_key_auth; void *security; struct user_struct *user; struct user_namespace *user_ns; struct group_info *group_info; struct callback_head rcu; } ; 369 struct seq_file { char *buf; size_t size; size_t from; size_t count; size_t pad_until; loff_t index; loff_t read_pos; u64 version; struct mutex lock; const struct seq_operations *op; int poll_event; const struct file *file; void *private; } ; 30 struct seq_operations { void * (*start)(struct seq_file *, loff_t *); void (*stop)(struct seq_file *, void *); void * (*next)(struct seq_file *, void *, loff_t *); int (*show)(struct seq_file *, void *); } ; 222 struct pinctrl ; 223 struct pinctrl_state ; 200 struct dev_pin_info { struct pinctrl *p; struct pinctrl_state *default_state; struct pinctrl_state *init_state; struct pinctrl_state *sleep_state; struct pinctrl_state *idle_state; } ; 58 struct pm_message { int event; } ; 64 typedef struct pm_message pm_message_t; 65 struct dev_pm_ops { int (*prepare)(struct device *); void (*complete)(struct device *); int (*suspend)(struct device *); int (*resume)(struct device *); int (*freeze)(struct device *); int (*thaw)(struct device *); int (*poweroff)(struct device *); int (*restore)(struct device *); int (*suspend_late)(struct device *); int (*resume_early)(struct device *); int (*freeze_late)(struct device *); int (*thaw_early)(struct device *); int (*poweroff_late)(struct device *); int (*restore_early)(struct device *); int (*suspend_noirq)(struct device *); int (*resume_noirq)(struct device *); int (*freeze_noirq)(struct device *); int (*thaw_noirq)(struct device *); int (*poweroff_noirq)(struct device *); int (*restore_noirq)(struct device *); int (*runtime_suspend)(struct device *); int (*runtime_resume)(struct device *); int (*runtime_idle)(struct device *); } ; 315 enum rpm_status { RPM_ACTIVE = 0, RPM_RESUMING = 1, RPM_SUSPENDED = 2, RPM_SUSPENDING = 3 } ; 322 enum rpm_request { RPM_REQ_NONE = 0, RPM_REQ_IDLE = 1, RPM_REQ_SUSPEND = 2, RPM_REQ_AUTOSUSPEND = 3, RPM_REQ_RESUME = 4 } ; 330 struct wakeup_source ; 331 struct wake_irq ; 332 struct pm_domain_data ; 333 struct pm_subsys_data { spinlock_t lock; unsigned int refcount; struct list_head clock_list; struct pm_domain_data *domain_data; } ; 551 struct dev_pm_qos ; 551 struct dev_pm_info { pm_message_t power_state; unsigned char can_wakeup; unsigned char async_suspend; bool in_dpm_list; bool is_prepared; bool is_suspended; bool is_noirq_suspended; bool is_late_suspended; bool early_init; bool direct_complete; spinlock_t lock; struct list_head entry; struct completion completion; struct wakeup_source *wakeup; bool wakeup_path; bool syscore; bool no_pm_callbacks; struct timer_list suspend_timer; unsigned long timer_expires; struct work_struct work; wait_queue_head_t wait_queue; struct wake_irq *wakeirq; atomic_t usage_count; atomic_t child_count; unsigned char disable_depth; unsigned char idle_notification; unsigned char request_pending; unsigned char deferred_resume; unsigned char runtime_auto; bool ignore_children; unsigned char no_callbacks; unsigned char irq_safe; unsigned char use_autosuspend; unsigned char timer_autosuspends; unsigned char memalloc_noio; unsigned int links_count; enum rpm_request request; enum rpm_status runtime_status; int runtime_error; int autosuspend_delay; unsigned long last_busy; unsigned long active_jiffies; unsigned long suspended_jiffies; unsigned long accounting_timestamp; struct pm_subsys_data *subsys_data; void (*set_latency_tolerance)(struct device *, s32 ); struct dev_pm_qos *qos; } ; 612 struct dev_pm_domain { struct dev_pm_ops ops; void (*detach)(struct device *, bool ); int (*activate)(struct device *); void (*sync)(struct device *); void (*dismiss)(struct device *); } ; 76 struct dev_archdata { void *iommu; } ; 8 struct dma_map_ops ; 18 struct pdev_archdata { } ; 21 struct device_private ; 22 struct device_driver ; 23 struct driver_private ; 24 struct class ; 25 struct subsys_private ; 26 struct bus_type ; 27 struct fwnode_handle ; 28 struct iommu_ops ; 29 struct iommu_group ; 30 struct iommu_fwspec ; 62 struct bus_type { const char *name; const char *dev_name; struct device *dev_root; const struct attribute_group **bus_groups; const struct attribute_group **dev_groups; const struct attribute_group **drv_groups; int (*match)(struct device *, struct device_driver *); int (*uevent)(struct device *, struct kobj_uevent_env *); int (*probe)(struct device *); int (*remove)(struct device *); void (*shutdown)(struct device *); int (*online)(struct device *); int (*offline)(struct device *); int (*suspend)(struct device *, pm_message_t ); int (*resume)(struct device *); int (*num_vf)(struct device *); const struct dev_pm_ops *pm; const struct iommu_ops *iommu_ops; struct subsys_private *p; struct lock_class_key lock_key; } ; 145 struct device_type ; 204 enum probe_type { PROBE_DEFAULT_STRATEGY = 0, PROBE_PREFER_ASYNCHRONOUS = 1, PROBE_FORCE_SYNCHRONOUS = 2 } ; 210 struct of_device_id ; 210 struct acpi_device_id ; 210 struct device_driver { const char *name; struct bus_type *bus; struct module *owner; const char *mod_name; bool suppress_bind_attrs; enum probe_type probe_type; const struct of_device_id *of_match_table; const struct acpi_device_id *acpi_match_table; int (*probe)(struct device *); int (*remove)(struct device *); void (*shutdown)(struct device *); int (*suspend)(struct device *, pm_message_t ); int (*resume)(struct device *); const struct attribute_group **groups; const struct dev_pm_ops *pm; struct driver_private *p; } ; 360 struct class { const char *name; struct module *owner; const struct attribute_group **class_groups; const struct attribute_group **dev_groups; struct kobject *dev_kobj; int (*dev_uevent)(struct device *, struct kobj_uevent_env *); char * (*devnode)(struct device *, umode_t *); void (*class_release)(struct class *); void (*dev_release)(struct device *); int (*suspend)(struct device *, pm_message_t ); int (*resume)(struct device *); int (*shutdown)(struct device *); const struct kobj_ns_type_operations *ns_type; const void * (*namespace)(struct device *); const struct dev_pm_ops *pm; struct subsys_private *p; } ; 523 struct device_type { const char *name; const struct attribute_group **groups; int (*uevent)(struct device *, struct kobj_uevent_env *); char * (*devnode)(struct device *, umode_t *, kuid_t *, kgid_t *); void (*release)(struct device *); const struct dev_pm_ops *pm; } ; 723 struct device_dma_parameters { unsigned int max_segment_size; unsigned long segment_boundary_mask; } ; 786 enum dl_dev_state { DL_DEV_NO_DRIVER = 0, DL_DEV_PROBING = 1, DL_DEV_DRIVER_BOUND = 2, DL_DEV_UNBINDING = 3 } ; 793 struct dev_links_info { struct list_head suppliers; struct list_head consumers; enum dl_dev_state status; } ; 813 struct irq_domain ; 813 struct dma_coherent_mem ; 813 struct cma ; 813 struct device { struct device *parent; struct device_private *p; struct kobject kobj; const char *init_name; const struct device_type *type; struct mutex mutex; struct bus_type *bus; struct device_driver *driver; void *platform_data; void *driver_data; struct dev_links_info links; struct dev_pm_info power; struct dev_pm_domain *pm_domain; struct irq_domain *msi_domain; struct dev_pin_info *pins; struct list_head msi_list; int numa_node; const struct dma_map_ops *dma_ops; u64 *dma_mask; u64 coherent_dma_mask; unsigned long dma_pfn_offset; struct device_dma_parameters *dma_parms; struct list_head dma_pools; struct dma_coherent_mem *dma_mem; struct cma *cma_area; struct dev_archdata archdata; struct device_node *of_node; struct fwnode_handle *fwnode; dev_t devt; u32 id; spinlock_t devres_lock; struct list_head devres_head; struct klist_node knode_class; struct class *class; const struct attribute_group **groups; void (*release)(struct device *); struct iommu_group *iommu_group; struct iommu_fwspec *iommu_fwspec; bool offline_disabled; bool offline; bool of_node_reused; } ; 975 struct wakeup_source { const char *name; struct list_head entry; spinlock_t lock; struct wake_irq *wakeirq; struct timer_list timer; unsigned long timer_expires; ktime_t total_time; ktime_t max_time; ktime_t last_time; ktime_t start_prevent_time; ktime_t prevent_sleep_time; unsigned long event_count; unsigned long active_count; unsigned long relax_count; unsigned long expire_count; unsigned long wakeup_count; bool active; bool autosleep_enabled; } ; 1455 struct tty_struct ; 105 struct tty_driver ; 105 struct console { char name[16U]; void (*write)(struct console *, const char *, unsigned int); int (*read)(struct console *, char *, unsigned int); struct tty_driver * (*device)(struct console *, int *); void (*unblank)(); int (*setup)(struct console *, char *); int (*match)(struct console *, char *, int, char *); short flags; short index; int cflag; void *data; struct console *next; } ; 216 enum irqreturn { IRQ_NONE = 0, IRQ_HANDLED = 1, IRQ_WAKE_THREAD = 2 } ; 16 typedef enum irqreturn irqreturn_t; 478 struct proc_dir_entry ; 133 struct exception_table_entry { int insn; int fixup; int handler; } ; 743 struct circ_buf { char *buf; int head; int tail; } ; 6 typedef unsigned char cc_t; 7 typedef unsigned int speed_t; 8 typedef unsigned int tcflag_t; 30 struct ktermios { tcflag_t c_iflag; tcflag_t c_oflag; tcflag_t c_cflag; tcflag_t c_lflag; cc_t c_line; cc_t c_cc[19U]; speed_t c_ispeed; speed_t c_ospeed; } ; 41 struct winsize { unsigned short ws_row; unsigned short ws_col; unsigned short ws_xpixel; unsigned short ws_ypixel; } ; 93 struct termiox { __u16 x_hflag; __u16 x_cflag; __u16 x_rflag[5U]; __u16 x_sflag; } ; 16 struct cdev { struct kobject kobj; struct module *owner; const struct file_operations *ops; struct list_head list; dev_t dev; unsigned int count; } ; 37 struct serial_icounter_struct ; 38 struct tty_operations { struct tty_struct * (*lookup)(struct tty_driver *, struct file *, int); int (*install)(struct tty_driver *, struct tty_struct *); void (*remove)(struct tty_driver *, struct tty_struct *); int (*open)(struct tty_struct *, struct file *); void (*close)(struct tty_struct *, struct file *); void (*shutdown)(struct tty_struct *); void (*cleanup)(struct tty_struct *); int (*write)(struct tty_struct *, const unsigned char *, int); int (*put_char)(struct tty_struct *, unsigned char); void (*flush_chars)(struct tty_struct *); int (*write_room)(struct tty_struct *); int (*chars_in_buffer)(struct tty_struct *); int (*ioctl)(struct tty_struct *, unsigned int, unsigned long); long int (*compat_ioctl)(struct tty_struct *, unsigned int, unsigned long); void (*set_termios)(struct tty_struct *, struct ktermios *); void (*throttle)(struct tty_struct *); void (*unthrottle)(struct tty_struct *); void (*stop)(struct tty_struct *); void (*start)(struct tty_struct *); void (*hangup)(struct tty_struct *); int (*break_ctl)(struct tty_struct *, int); void (*flush_buffer)(struct tty_struct *); void (*set_ldisc)(struct tty_struct *); void (*wait_until_sent)(struct tty_struct *, int); void (*send_xchar)(struct tty_struct *, char); int (*tiocmget)(struct tty_struct *); int (*tiocmset)(struct tty_struct *, unsigned int, unsigned int); int (*resize)(struct tty_struct *, struct winsize *); int (*set_termiox)(struct tty_struct *, struct termiox *); int (*get_icount)(struct tty_struct *, struct serial_icounter_struct *); int (*poll_init)(struct tty_driver *, int, char *); int (*poll_get_char)(struct tty_driver *, int); void (*poll_put_char)(struct tty_driver *, int, char); const struct file_operations *proc_fops; } ; 295 struct tty_port ; 295 struct tty_driver { int magic; struct kref kref; struct cdev **cdevs; struct module *owner; const char *driver_name; const char *name; int name_base; int major; int minor_start; unsigned int num; short type; short subtype; struct ktermios init_termios; unsigned long flags; struct proc_dir_entry *proc_entry; struct tty_driver *other; struct tty_struct **ttys; struct tty_port **ports; struct ktermios **termios; void *driver_state; const struct tty_operations *ops; struct list_head tty_drivers; } ; 362 struct ld_semaphore { long count; raw_spinlock_t wait_lock; unsigned int wait_readers; struct list_head read_wait; struct list_head write_wait; struct lockdep_map dep_map; } ; 159 struct tty_ldisc_ops { int magic; char *name; int num; int flags; int (*open)(struct tty_struct *); void (*close)(struct tty_struct *); void (*flush_buffer)(struct tty_struct *); ssize_t (*read)(struct tty_struct *, struct file *, unsigned char *, size_t ); ssize_t (*write)(struct tty_struct *, struct file *, const unsigned char *, size_t ); int (*ioctl)(struct tty_struct *, struct file *, unsigned int, unsigned long); long int (*compat_ioctl)(struct tty_struct *, struct file *, unsigned int, unsigned long); void (*set_termios)(struct tty_struct *, struct ktermios *); unsigned int (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *); int (*hangup)(struct tty_struct *); void (*receive_buf)(struct tty_struct *, const unsigned char *, char *, int); void (*write_wakeup)(struct tty_struct *); void (*dcd_change)(struct tty_struct *, unsigned int); int (*receive_buf2)(struct tty_struct *, const unsigned char *, char *, int); struct module *owner; int refcount; } ; 207 struct tty_ldisc { struct tty_ldisc_ops *ops; struct tty_struct *tty; } ; 217 union __anonunion____missing_field_name_362 { struct tty_buffer *next; struct llist_node free; } ; 217 struct tty_buffer { union __anonunion____missing_field_name_362 __annonCompField81; int used; int size; int commit; int read; int flags; unsigned long data[0U]; } ; 82 struct tty_bufhead { struct tty_buffer *head; struct work_struct work; struct mutex lock; atomic_t priority; struct tty_buffer sentinel; struct llist_head free; atomic_t mem_used; int mem_limit; struct tty_buffer *tail; } ; 94 struct tty_port_operations { int (*carrier_raised)(struct tty_port *); void (*dtr_rts)(struct tty_port *, int); void (*shutdown)(struct tty_port *); int (*activate)(struct tty_port *, struct tty_struct *); void (*destruct)(struct tty_port *); } ; 220 struct tty_port_client_operations { int (*receive_buf)(struct tty_port *, const unsigned char *, const unsigned char *, size_t ); void (*write_wakeup)(struct tty_port *); } ; 225 struct tty_port { struct tty_bufhead buf; struct tty_struct *tty; struct tty_struct *itty; const struct tty_port_operations *ops; const struct tty_port_client_operations *client_ops; spinlock_t lock; int blocked_open; int count; wait_queue_head_t open_wait; wait_queue_head_t delta_msr_wait; unsigned long flags; unsigned long iflags; unsigned char console; unsigned char low_latency; struct mutex mutex; struct mutex buf_mutex; unsigned char *xmit_buf; unsigned int close_delay; unsigned int closing_wait; int drain_delay; struct kref kref; void *client_data; } ; 252 struct tty_struct { int magic; struct kref kref; struct device *dev; struct tty_driver *driver; const struct tty_operations *ops; int index; struct ld_semaphore ldisc_sem; struct tty_ldisc *ldisc; struct mutex atomic_write_lock; struct mutex legacy_mutex; struct mutex throttle_mutex; struct rw_semaphore termios_rwsem; struct mutex winsize_mutex; spinlock_t ctrl_lock; spinlock_t flow_lock; struct ktermios termios; struct ktermios termios_locked; struct termiox *termiox; char name[64U]; struct pid *pgrp; struct pid *session; unsigned long flags; int count; struct winsize winsize; unsigned char stopped; unsigned char flow_stopped; unsigned long unused; int hw_stopped; unsigned char ctrl_status; unsigned char packet; unsigned long unused_ctrl; unsigned int receive_room; int flow_change; struct tty_struct *link; struct fasync_struct *fasync; wait_queue_head_t write_wait; wait_queue_head_t read_wait; struct work_struct hangup_work; void *disc_data; void *driver_data; spinlock_t files_lock; struct list_head tty_files; int closing; unsigned char *write_buf; int write_cnt; struct work_struct SAK_work; struct tty_port *port; } ; 52 struct serial_struct { int type; int line; unsigned int port; int irq; int flags; int xmit_fifo_size; int custom_divisor; int baud_base; unsigned short close_delay; char io_type; char reserved_char[1U]; int hub6; unsigned short closing_wait; unsigned short closing_wait2; unsigned char *iomem_base; unsigned short iomem_reg_shift; unsigned int port_high; unsigned long iomap_base; } ; 96 struct serial_icounter_struct { int cts; int dsr; int rng; int dcd; int rx; int tx; int frame; int overrun; int parity; int brk; int buf_overrun; int reserved[9U]; } ; 108 struct serial_rs485 { __u32 flags; __u32 delay_rts_before_send; __u32 delay_rts_after_send; __u32 padding[5U]; } ; 25 struct uart_port ; 26 struct uart_ops { unsigned int (*tx_empty)(struct uart_port *); void (*set_mctrl)(struct uart_port *, unsigned int); unsigned int (*get_mctrl)(struct uart_port *); void (*stop_tx)(struct uart_port *); void (*start_tx)(struct uart_port *); void (*throttle)(struct uart_port *); void (*unthrottle)(struct uart_port *); void (*send_xchar)(struct uart_port *, char); void (*stop_rx)(struct uart_port *); void (*enable_ms)(struct uart_port *); void (*break_ctl)(struct uart_port *, int); int (*startup)(struct uart_port *); void (*shutdown)(struct uart_port *); void (*flush_buffer)(struct uart_port *); void (*set_termios)(struct uart_port *, struct ktermios *, struct ktermios *); void (*set_ldisc)(struct uart_port *, struct ktermios *); void (*pm)(struct uart_port *, unsigned int, unsigned int); const char * (*type)(struct uart_port *); void (*release_port)(struct uart_port *); int (*request_port)(struct uart_port *); void (*config_port)(struct uart_port *, int); int (*verify_port)(struct uart_port *, struct serial_struct *); int (*ioctl)(struct uart_port *, unsigned int, unsigned long); int (*poll_init)(struct uart_port *); void (*poll_put_char)(struct uart_port *, unsigned char); int (*poll_get_char)(struct uart_port *); } ; 94 struct uart_icount { __u32 cts; __u32 dsr; __u32 rng; __u32 dcd; __u32 rx; __u32 tx; __u32 frame; __u32 overrun; __u32 parity; __u32 brk; __u32 buf_overrun; } ; 114 typedef unsigned int upf_t; 115 typedef unsigned int upstat_t; 116 struct uart_state ; 116 struct uart_port { spinlock_t lock; unsigned long iobase; unsigned char *membase; unsigned int (*serial_in)(struct uart_port *, int); void (*serial_out)(struct uart_port *, int, int); void (*set_termios)(struct uart_port *, struct ktermios *, struct ktermios *); void (*set_ldisc)(struct uart_port *, struct ktermios *); unsigned int (*get_mctrl)(struct uart_port *); void (*set_mctrl)(struct uart_port *, unsigned int); int (*startup)(struct uart_port *); void (*shutdown)(struct uart_port *); void (*throttle)(struct uart_port *); void (*unthrottle)(struct uart_port *); int (*handle_irq)(struct uart_port *); void (*pm)(struct uart_port *, unsigned int, unsigned int); void (*handle_break)(struct uart_port *); int (*rs485_config)(struct uart_port *, struct serial_rs485 *); unsigned int irq; unsigned long irqflags; unsigned int uartclk; unsigned int fifosize; unsigned char x_char; unsigned char regshift; unsigned char iotype; unsigned char unused1; unsigned int read_status_mask; unsigned int ignore_status_mask; struct uart_state *state; struct uart_icount icount; struct console *cons; unsigned long sysrq; upf_t flags; upstat_t status; int hw_stopped; unsigned int mctrl; unsigned int timeout; unsigned int type; const struct uart_ops *ops; unsigned int custom_divisor; unsigned int line; unsigned int minor; resource_size_t mapbase; resource_size_t mapsize; struct device *dev; unsigned char hub6; unsigned char suspended; unsigned char irq_wake; unsigned char unused[2U]; const char *name; struct attribute_group *attr_group; const struct attribute_group **tty_groups; struct serial_rs485 rs485; void *private_data; } ; 267 enum uart_pm_state { UART_PM_STATE_ON = 0, UART_PM_STATE_OFF = 3, UART_PM_STATE_UNDEFINED = 4 } ; 273 struct uart_state { struct tty_port port; enum uart_pm_state pm_state; struct circ_buf xmit; atomic_t refcount; wait_queue_head_t remove_wait; struct uart_port *uart_port; } ; 293 struct uart_driver { struct module *owner; const char *driver_name; const char *dev_name; int major; int minor; int nr; struct console *cons; struct uart_state *state; struct tty_driver *tty_driver; } ; 13 typedef unsigned long kernel_ulong_t; 187 struct acpi_device_id { __u8 id[9U]; kernel_ulong_t driver_data; __u32 cls; __u32 cls_msk; } ; 230 struct of_device_id { char name[32U]; char type[32U]; char compatible[128U]; const void *data; } ; 496 struct platform_device_id { char name[20U]; kernel_ulong_t driver_data; } ; 687 struct mfd_cell ; 689 struct platform_device { const char *name; int id; bool id_auto; struct device dev; u32 num_resources; struct resource *resource; const struct platform_device_id *id_entry; char *driver_override; struct mfd_cell *mfd_cell; struct pdev_archdata archdata; } ; 352 struct sccnxp_pdata { const u8 reg_shift; const u32 mctrl_cfg[2U]; const unsigned int poll_time_us; } ; 155 struct regulator ; 610 struct sccnxp_chip { const char *name; unsigned int nr; unsigned long freq_min; unsigned long freq_std; unsigned long freq_max; unsigned int flags; unsigned int fifosize; } ; 111 struct sccnxp_port { struct uart_driver uart; struct uart_port port[2U]; bool opened[2U]; int irq; u8 imr; struct sccnxp_chip *chip; spinlock_t lock; bool poll; struct timer_list timer; struct sccnxp_pdata pdata; struct regulator *regulator; } ; 253 struct __anonstruct_baud_std_364 { u8 csr; u8 acr; u8 mr0; int baud; } ; 1 long int __builtin_expect(long, long); 34 extern struct module __this_module; 63 void __dynamic_dev_dbg(struct _ddebug *, const struct device *, const char *, ...); 3 bool ldv_is_err(const void *ptr); 6 long int ldv_ptr_err(const void *ptr); 32 void * __memcpy(void *, const void *, size_t ); 32 long int PTR_ERR(const void *ptr); 41 bool IS_ERR(const void *ptr); 93 void __raw_spin_lock_init(raw_spinlock_t *, const char *, struct lock_class_key *); 32 unsigned long int _raw_spin_lock_irqsave(raw_spinlock_t *); 43 void _raw_spin_unlock_irqrestore(raw_spinlock_t *, unsigned long); 286 raw_spinlock_t * spinlock_check(spinlock_t *lock); 352 void spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags); 77 extern volatile unsigned long jiffies; 370 unsigned long int __usecs_to_jiffies(const unsigned int); 406 unsigned long int usecs_to_jiffies(const unsigned int u); 92 void init_timer_key(struct timer_list *, unsigned int, const char *, struct lock_class_key *); 188 int mod_timer(struct timer_list *, unsigned long); 202 int del_timer_sync(struct timer_list *); 56 unsigned char readb(const volatile void *addr); 64 void writeb(unsigned char val, volatile void *addr); 87 const char * kobject_name(const struct kobject *kobj); 11 void ldv_clk_disable_clk(struct clk *clk); 12 int ldv_clk_enable_clk(); 316 struct clk * devm_clk_get(struct device *, const char *); 348 int ldv_clk_enable_5(struct clk *clk); 376 void ldv_clk_disable_6(struct clk *clk); 398 unsigned long int clk_get_rate(struct clk *); 657 int ldv_clk_prepare_enable_7(struct clk *clk); 656 void * devm_kmalloc(struct device *, size_t , gfp_t ); 662 void * devm_kzalloc(struct device *dev, size_t size, gfp_t gfp); 687 void * devm_ioremap_resource(struct device *, struct resource *); 978 const char * dev_name(const struct device *dev); 1025 void * dev_get_drvdata(const struct device *dev); 1030 void dev_set_drvdata(struct device *dev, void *data); 1167 void * dev_get_platdata(const struct device *dev); 1260 void dev_err(const struct device *, const char *, ...); 1264 void dev_notice(const struct device *, const char *, ...); 1266 void _dev_info(const struct device *, const char *, ...); 173 int devm_request_threaded_irq(struct device *, unsigned int, irqreturn_t (*)(int, void *), irqreturn_t (*)(int, void *), unsigned long, const char *, void *); 191 void devm_free_irq(struct device *, unsigned int, void *); 487 void do_SAK(struct tty_struct *); 500 speed_t tty_termios_baud_rate(struct ktermios *); 502 void tty_termios_encode_baud_rate(struct ktermios *, speed_t , speed_t ); 320 void uart_write_wakeup(struct uart_port *); 325 void uart_update_timeout(struct uart_port *, unsigned int, unsigned int); 327 unsigned int uart_get_baud_rate(struct uart_port *, struct ktermios *, struct ktermios *, unsigned int, unsigned int); 402 int uart_register_driver(struct uart_driver *); 403 void uart_unregister_driver(struct uart_driver *); 404 int uart_add_one_port(struct uart_driver *, struct uart_port *); 405 int uart_remove_one_port(struct uart_driver *, struct uart_port *); 423 int uart_tx_stopped(struct uart_port *port); 452 void uart_insert_char(struct uart_port *, unsigned int, unsigned int, unsigned int, unsigned int); 476 int uart_handle_break(struct uart_port *port); 13 void tty_flip_buffer_push(struct tty_port *); 52 struct resource * platform_get_resource(struct platform_device *, unsigned int, unsigned int); 54 int platform_get_irq(struct platform_device *, unsigned int); 211 void * platform_get_drvdata(const struct platform_device *pdev); 216 void platform_set_drvdata(struct platform_device *pdev, void *data); 183 struct regulator * devm_regulator_get(struct device *, const char *); 225 int regulator_enable(struct regulator *); 226 int regulator_disable(struct regulator *); 216 u8 sccnxp_read(struct uart_port *port, u8 reg); 221 void sccnxp_write(struct uart_port *port, u8 reg, u8 v); 226 u8 sccnxp_port_read(struct uart_port *port, u8 reg); 231 void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v); 236 int sccnxp_update_best_err(int a, int b, int *besterr); 253 const struct __anonstruct_baud_std_364 baud_std[29U] = { { 0U, 0U, 0U, 50 }, { 0U, 128U, 0U, 75 }, { 1U, 0U, 0U, 110 }, { 2U, 0U, 0U, 134 }, { 3U, 128U, 0U, 150 }, { 3U, 0U, 0U, 200 }, { 4U, 0U, 0U, 300 }, { 0U, 128U, 1U, 450 }, { 1U, 0U, 5U, 880 }, { 3U, 128U, 1U, 900 }, { 5U, 0U, 0U, 600 }, { 7U, 0U, 0U, 1050 }, { 2U, 0U, 5U, 1076 }, { 6U, 0U, 0U, 1200 }, { 10U, 128U, 0U, 1800 }, { 7U, 128U, 0U, 2000 }, { 8U, 0U, 0U, 2400 }, { 5U, 128U, 1U, 3600 }, { 9U, 0U, 0U, 4800 }, { 10U, 0U, 0U, 7200 }, { 11U, 0U, 0U, 9600 }, { 8U, 0U, 1U, 14400 }, { 12U, 128U, 0U, 19200 }, { 9U, 0U, 1U, 28800 }, { 12U, 0U, 0U, 38400 }, { 11U, 0U, 1U, 57600 }, { 12U, 128U, 1U, 115200 }, { 12U, 0U, 1U, 230400 }, { 0U, 0U, 0U, 0 } }; 285 int sccnxp_set_baud(struct uart_port *port, int baud); 324 void sccnxp_enable_irq(struct uart_port *port, int mask); 332 void sccnxp_disable_irq(struct uart_port *port, int mask); 340 void sccnxp_set_bit(struct uart_port *port, int sig, int state); 354 void sccnxp_handle_rx(struct uart_port *port); 410 void sccnxp_handle_tx(struct uart_port *port); 449 void sccnxp_handle_events(struct sccnxp_port *s); 469 void sccnxp_timer(unsigned long data); 481 irqreturn_t sccnxp_ist(int irq, void *dev_id); 493 void sccnxp_start_tx(struct uart_port *port); 509 void sccnxp_stop_tx(struct uart_port *port); 514 void sccnxp_stop_rx(struct uart_port *port); 524 unsigned int sccnxp_tx_empty(struct uart_port *port); 537 void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl); 553 unsigned int sccnxp_get_mctrl(struct uart_port *port); 597 void sccnxp_break_ctl(struct uart_port *port, int break_state); 608 void sccnxp_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old); 695 int sccnxp_startup(struct uart_port *port); 726 void sccnxp_shutdown(struct uart_port *port); 748 const char * sccnxp_type(struct uart_port *port); 755 void sccnxp_release_port(struct uart_port *port); 760 int sccnxp_request_port(struct uart_port *port); 766 void sccnxp_config_port(struct uart_port *port, int flags); 772 int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s); 782 const struct uart_ops sccnxp_ops = { &sccnxp_tx_empty, &sccnxp_set_mctrl, &sccnxp_get_mctrl, &sccnxp_stop_tx, &sccnxp_start_tx, 0, 0, 0, &sccnxp_stop_rx, 0, &sccnxp_break_ctl, &sccnxp_startup, &sccnxp_shutdown, 0, &sccnxp_set_termios, 0, 0, &sccnxp_type, &sccnxp_release_port, &sccnxp_request_port, &sccnxp_config_port, &sccnxp_verify_port, 0, 0, 0, 0 }; 849 const struct platform_device_id __mod_platform__sccnxp_id_table_device_table[9U] = { }; 851 int sccnxp_probe(struct platform_device *pdev); 997 int sccnxp_remove(struct platform_device *pdev); 1048 void ldv_check_final_state(); 1051 void ldv_check_return_value(int); 1054 void ldv_check_return_value_probe(int); 1057 void ldv_initialize(); 1060 void ldv_handler_precall(); 1063 int nondet_int(); 1066 int LDV_IN_INTERRUPT = 0; 1069 void ldv_main0_sequence_infinite_withcheck_stateful(); 10 void ldv_error(); 25 int ldv_undef_int(); 14 void * ldv_err_ptr(long error); 28 bool ldv_is_err_or_null(const void *ptr); 9 int ldv_counter_clk = 0; return ; } { 1071 struct uart_port *var_group1; 1072 unsigned int var_sccnxp_set_mctrl_18_p1; 1073 int var_sccnxp_break_ctl_20_p1; 1074 struct ktermios *var_group2; 1075 struct ktermios *var_sccnxp_set_termios_21_p2; 1076 int var_sccnxp_config_port_27_p1; 1077 struct serial_struct *var_group3; 1078 struct platform_device *var_group4; 1079 int res_sccnxp_probe_32; 1080 int var_sccnxp_ist_13_p0; 1081 void *var_sccnxp_ist_13_p1; 1082 int ldv_s_sccnxp_uart_driver_platform_driver; 1083 int tmp; 1084 int tmp___0; 2501 ldv_s_sccnxp_uart_driver_platform_driver = 0; 2489 LDV_IN_INTERRUPT = 1; 2498 ldv_initialize() { /* Function call is skipped due to function is undefined */} 2506 goto ldv_31265; 2506 tmp___0 = nondet_int() { /* Function call is skipped due to function is undefined */} 2509 goto ldv_31264; 2507 ldv_31264:; 2510 tmp = nondet_int() { /* Function call is skipped due to function is undefined */} 2510 switch (tmp); { 853 struct resource *res; 854 struct resource *tmp; 855 struct sccnxp_pdata *pdata; 856 void *tmp___0; 857 int i; 858 int ret; 859 int uartclk; 860 struct sccnxp_port *s; 861 void *membase; 862 struct clk *clk; 863 long tmp___1; 864 _Bool tmp___2; 865 void *tmp___3; 866 struct lock_class_key __key; 867 long tmp___4; 868 _Bool tmp___5; 869 int tmp___6; 870 long tmp___7; 871 unsigned long tmp___8; 872 _Bool tmp___9; 873 const char *tmp___10; 874 struct lock_class_key __key___0; 875 struct lock_class_key __key___1; 876 unsigned long tmp___11; 877 int tmp___12; 878 _Bool tmp___13; 879 int tmp___14; 853 tmp = platform_get_resource(pdev, 512U, 0U) { /* Function call is skipped due to function is undefined */} 853 res = tmp; { 1169 void *__CPAchecker_TMP_0 = (void *)(dev->platform_data); 1169 return __CPAchecker_TMP_0;; } 854 pdata = (struct sccnxp_pdata *)tmp___0; 860 membase = devm_ioremap_resource(&(pdev->dev), res) { /* Function call is skipped due to function is undefined */} { 664 void *tmp; 664 tmp = devm_kmalloc(dev, size, gfp | 32768U) { /* Function call is skipped due to function is undefined */} 664 return tmp;; } 864 s = (struct sccnxp_port *)tmp___3; { { 1032 dev->driver_data = data; 1033 return ;; } 220 return ;; } { 288 return &(lock->__annonCompField21.rlock);; } 871 __raw_spin_lock_init(&(s->lock.__annonCompField21.rlock), "&(&s->lock)->rlock", &__key) { /* Function call is skipped due to function is undefined */} 873 struct sccnxp_chip *__CPAchecker_TMP_0 = (struct sccnxp_chip *)(pdev->id_entry->driver_data); 873 s->chip = __CPAchecker_TMP_0; 875 s->regulator = devm_regulator_get(&(pdev->dev), "vcc") { /* Function call is skipped due to function is undefined */} 876 const void *__CPAchecker_TMP_1 = (const void *)(s->regulator); 876 tmp___6 = 1; 877 ret = regulator_enable(s->regulator) { /* Function call is skipped due to function is undefined */} 886 clk = devm_clk_get(&(pdev->dev), (const char *)0) { /* Function call is skipped due to function is undefined */} { 52 int tmp; { } 21 int retval; 22 int tmp; 21 tmp = ldv_undef_int() { /* Function call is skipped due to function is undefined */} 21 retval = tmp; 25 ldv_counter_clk = 1; } 894 tmp___8 = clk_get_rate(clk) { /* Function call is skipped due to function is undefined */} 894 uartclk = (int)tmp___8; 910 __memcpy((void *)(&(s->pdata)), (const void *)pdata, 16UL) { /* Function call is skipped due to function is undefined */} 919 s->irq = platform_get_irq(pdev, 0U) { /* Function call is skipped due to function is undefined */} 927 s->uart.owner = &__this_module; 928 s->uart.dev_name = "ttySC"; 929 s->uart.major = 204; 930 s->uart.minor = 205; 931 int __CPAchecker_TMP_4 = (int)(s->chip->nr); 931 s->uart.nr = __CPAchecker_TMP_4; 942 ret = uart_register_driver(&(s->uart)) { /* Function call is skipped due to function is undefined */} 948 i = 0; 948 goto ldv_31183; 968 s->imr = 0U; { 223 volatile void *__CPAchecker_TMP_0 = (volatile void *)(port->membase); 223 int __CPAchecker_TMP_1 = (int)(port->regshift); { }64 Ignored inline assembler code 65 return ;; } { 980 const char *tmp; 981 unsigned long __CPAchecker_TMP_0 = (unsigned long)(dev->init_name); 981 assume(!(__CPAchecker_TMP_0 != ((unsigned long)((const char *)0)))); { 89 const char *__CPAchecker_TMP_0 = (const char *)(kobj->name); 89 return __CPAchecker_TMP_0;; } 984 return tmp;; } 972 unsigned int __CPAchecker_TMP_7 = (unsigned int)(s->irq); 972 ret = devm_request_threaded_irq(&(pdev->dev), __CPAchecker_TMP_7, (irqreturn_t (*)(int, void *))0, &sccnxp_ist, 8194UL, tmp___10, (void *)s) { /* Function call is skipped due to function is undefined */} 980 dev_err((const struct device *)(&(pdev->dev)), "Unable to reguest IRQ %i\n", s->irq) { /* Function call is skipped due to function is undefined */} 989 uart_unregister_driver(&(s->uart)) { /* Function call is skipped due to function is undefined */} 990 err_out:; 991 const void *__CPAchecker_TMP_8 = (const void *)(s->regulator); 991 tmp___14 = 1; 992 tmp___12 = regulator_disable(s->regulator) { /* Function call is skipped due to function is undefined */} } 3972 ldv_check_return_value(res_sccnxp_probe_32) { /* Function call is skipped due to function is undefined */} 3973 ldv_check_return_value_probe(res_sccnxp_probe_32) { /* Function call is skipped due to function is undefined */} 3975 goto ldv_module_exit; } | Source code
1 #ifndef _ASM_X86_IO_H
2 #define _ASM_X86_IO_H
3
4 /*
5 * This file contains the definitions for the x86 IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
9 *
10 * This file is not meant to be obfuscating: it's just complicated
11 * to (a) handle it all in a way that makes gcc able to optimize it
12 * as well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
14 * mistake somewhere.
15 */
16
17 /*
18 * Thanks to James van Artsdalen for a better timing-fix than
19 * the two short jumps: using outb's to a nonexistent port seems
20 * to guarantee better timings even on fast machines.
21 *
22 * On the other hand, I'd like to be sure of a non-existent port:
23 * I feel a bit unsafe about using 0x80 (should be safe, though)
24 *
25 * Linus
26 */
27
28 /*
29 * Bit simplified and optimized by Jan Hubicka
30 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
31 *
32 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
33 * isa_read[wl] and isa_write[wl] fixed
34 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
35 */
36
37 #define ARCH_HAS_IOREMAP_WC
38 #define ARCH_HAS_IOREMAP_WT
39
40 #include <linux/string.h>
41 #include <linux/compiler.h>
42 #include <asm/page.h>
43 #include <asm/early_ioremap.h>
44 #include <asm/pgtable_types.h>
45
46 #define build_mmio_read(name, size, type, reg, barrier) \
47 static inline type name(const volatile void __iomem *addr) \
48 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
49 :"m" (*(volatile type __force *)addr) barrier); return ret; }
50
51 #define build_mmio_write(name, size, type, reg, barrier) \
52 static inline void name(type val, volatile void __iomem *addr) \
53 { asm volatile("mov" size " %0,%1": :reg (val), \
54 "m" (*(volatile type __force *)addr) barrier); }
55
56 build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
57 build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
58 build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
59
60 build_mmio_read(__readb, "b", unsigned char, "=q", )
61 build_mmio_read(__readw, "w", unsigned short, "=r", )
62 build_mmio_read(__readl, "l", unsigned int, "=r", )
63
64 build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
65 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
66 build_mmio_write(writel, "l", unsigned int, "r", :"memory")
67
68 build_mmio_write(__writeb, "b", unsigned char, "q", )
69 build_mmio_write(__writew, "w", unsigned short, "r", )
70 build_mmio_write(__writel, "l", unsigned int, "r", )
71
72 #define readb_relaxed(a) __readb(a)
73 #define readw_relaxed(a) __readw(a)
74 #define readl_relaxed(a) __readl(a)
75 #define __raw_readb __readb
76 #define __raw_readw __readw
77 #define __raw_readl __readl
78
79 #define writeb_relaxed(v, a) __writeb(v, a)
80 #define writew_relaxed(v, a) __writew(v, a)
81 #define writel_relaxed(v, a) __writel(v, a)
82 #define __raw_writeb __writeb
83 #define __raw_writew __writew
84 #define __raw_writel __writel
85
86 #define mmiowb() barrier()
87
88 #ifdef CONFIG_X86_64
89
90 build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
91 build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
92
93 #define readq_relaxed(a) readq(a)
94 #define writeq_relaxed(v, a) writeq(v, a)
95
96 #define __raw_readq(a) readq(a)
97 #define __raw_writeq(val, addr) writeq(val, addr)
98
99 /* Let people know that we have them */
100 #define readq readq
101 #define writeq writeq
102
103 #endif
104
105 /**
106 * virt_to_phys - map virtual addresses to physical
107 * @address: address to remap
108 *
109 * The returned physical address is the physical (CPU) mapping for
110 * the memory address given. It is only valid to use this function on
111 * addresses directly mapped or allocated via kmalloc.
112 *
113 * This function does not give bus mappings for DMA transfers. In
114 * almost all conceivable cases a device driver should not be using
115 * this function
116 */
117
118 static inline phys_addr_t virt_to_phys(volatile void *address)
119 {
120 return __pa(address);
121 }
122
123 /**
124 * phys_to_virt - map physical address to virtual
125 * @address: address to remap
126 *
127 * The returned virtual address is a current CPU mapping for
128 * the memory address given. It is only valid to use this function on
129 * addresses that have a kernel mapping
130 *
131 * This function does not handle bus mappings for DMA transfers. In
132 * almost all conceivable cases a device driver should not be using
133 * this function
134 */
135
136 static inline void *phys_to_virt(phys_addr_t address)
137 {
138 return __va(address);
139 }
140
141 /*
142 * Change "struct page" to physical address.
143 */
144 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
145
146 /*
147 * ISA I/O bus memory addresses are 1:1 with the physical address.
148 * However, we truncate the address to unsigned int to avoid undesirable
149 * promitions in legacy drivers.
150 */
151 static inline unsigned int isa_virt_to_bus(volatile void *address)
152 {
153 return (unsigned int)virt_to_phys(address);
154 }
155 #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page))
156 #define isa_bus_to_virt phys_to_virt
157
158 /*
159 * However PCI ones are not necessarily 1:1 and therefore these interfaces
160 * are forbidden in portable PCI drivers.
161 *
162 * Allow them on x86 for legacy drivers, though.
163 */
164 #define virt_to_bus virt_to_phys
165 #define bus_to_virt phys_to_virt
166
167 /*
168 * The default ioremap() behavior is non-cached; if you need something
169 * else, you probably want one of the following.
170 */
171 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
172 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size);
173 #define ioremap_uc ioremap_uc
174
175 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
176 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val);
177
178 /**
179 * ioremap - map bus memory into CPU space
180 * @offset: bus address of the memory
181 * @size: size of the resource to map
182 *
183 * ioremap performs a platform specific sequence of operations to
184 * make bus memory CPU accessible via the readb/readw/readl/writeb/
185 * writew/writel functions and the other mmio helpers. The returned
186 * address is not guaranteed to be usable directly as a virtual
187 * address.
188 *
189 * If the area you are trying to map is a PCI BAR you should have a
190 * look at pci_iomap().
191 */
192 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
193 {
194 return ioremap_nocache(offset, size);
195 }
196
197 extern void iounmap(volatile void __iomem *addr);
198
199 extern void set_iounmap_nonlazy(void);
200
201 #ifdef __KERNEL__
202
203 #include <asm-generic/iomap.h>
204
205 /*
206 * Convert a virtual cached pointer to an uncached pointer
207 */
208 #define xlate_dev_kmem_ptr(p) p
209
210 /**
211 * memset_io Set a range of I/O memory to a constant value
212 * @addr: The beginning of the I/O-memory range to set
213 * @val: The value to set the memory to
214 * @count: The number of bytes to set
215 *
216 * Set a range of I/O memory to a given value.
217 */
218 static inline void
219 memset_io(volatile void __iomem *addr, unsigned char val, size_t count)
220 {
221 memset((void __force *)addr, val, count);
222 }
223
224 /**
225 * memcpy_fromio Copy a block of data from I/O memory
226 * @dst: The (RAM) destination for the copy
227 * @src: The (I/O memory) source for the data
228 * @count: The number of bytes to copy
229 *
230 * Copy a block of data from I/O memory.
231 */
232 static inline void
233 memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count)
234 {
235 memcpy(dst, (const void __force *)src, count);
236 }
237
238 /**
239 * memcpy_toio Copy a block of data into I/O memory
240 * @dst: The (I/O memory) destination for the copy
241 * @src: The (RAM) source for the data
242 * @count: The number of bytes to copy
243 *
244 * Copy a block of data to I/O memory.
245 */
246 static inline void
247 memcpy_toio(volatile void __iomem *dst, const void *src, size_t count)
248 {
249 memcpy((void __force *)dst, src, count);
250 }
251
252 /*
253 * ISA space is 'always mapped' on a typical x86 system, no need to
254 * explicitly ioremap() it. The fact that the ISA IO space is mapped
255 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
256 * are physical addresses. The following constant pointer can be
257 * used as the IO-area pointer (it can be iounmapped as well, so the
258 * analogy with PCI is quite large):
259 */
260 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
261
262 /*
263 * Cache management
264 *
265 * This needed for two cases
266 * 1. Out of order aware processors
267 * 2. Accidentally out of order processors (PPro errata #51)
268 */
269
270 static inline void flush_write_buffers(void)
271 {
272 #if defined(CONFIG_X86_PPRO_FENCE)
273 asm volatile("lock; addl $0,0(%%esp)": : :"memory");
274 #endif
275 }
276
277 #endif /* __KERNEL__ */
278
279 extern void native_io_delay(void);
280
281 extern int io_delay_type;
282 extern void io_delay_init(void);
283
284 #if defined(CONFIG_PARAVIRT)
285 #include <asm/paravirt.h>
286 #else
287
288 static inline void slow_down_io(void)
289 {
290 native_io_delay();
291 #ifdef REALLY_SLOW_IO
292 native_io_delay();
293 native_io_delay();
294 native_io_delay();
295 #endif
296 }
297
298 #endif
299
300 #define BUILDIO(bwl, bw, type) \
301 static inline void out##bwl(unsigned type value, int port) \
302 { \
303 asm volatile("out" #bwl " %" #bw "0, %w1" \
304 : : "a"(value), "Nd"(port)); \
305 } \
306 \
307 static inline unsigned type in##bwl(int port) \
308 { \
309 unsigned type value; \
310 asm volatile("in" #bwl " %w1, %" #bw "0" \
311 : "=a"(value) : "Nd"(port)); \
312 return value; \
313 } \
314 \
315 static inline void out##bwl##_p(unsigned type value, int port) \
316 { \
317 out##bwl(value, port); \
318 slow_down_io(); \
319 } \
320 \
321 static inline unsigned type in##bwl##_p(int port) \
322 { \
323 unsigned type value = in##bwl(port); \
324 slow_down_io(); \
325 return value; \
326 } \
327 \
328 static inline void outs##bwl(int port, const void *addr, unsigned long count) \
329 { \
330 asm volatile("rep; outs" #bwl \
331 : "+S"(addr), "+c"(count) : "d"(port)); \
332 } \
333 \
334 static inline void ins##bwl(int port, void *addr, unsigned long count) \
335 { \
336 asm volatile("rep; ins" #bwl \
337 : "+D"(addr), "+c"(count) : "d"(port)); \
338 }
339
340 BUILDIO(b, b, char)
341 BUILDIO(w, w, short)
342 BUILDIO(l, , int)
343
344 extern void *xlate_dev_mem_ptr(phys_addr_t phys);
345 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
346
347 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
348 enum page_cache_mode pcm);
349 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
350 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size);
351
352 extern bool is_early_ioremap_ptep(pte_t *ptep);
353
354 #ifdef CONFIG_XEN
355 #include <xen/xen.h>
356 struct bio_vec;
357
358 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
359 const struct bio_vec *vec2);
360
361 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
362 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
363 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
364 #endif /* CONFIG_XEN */
365
366 #define IO_SPACE_LIMIT 0xffff
367
368 #ifdef CONFIG_MTRR
369 extern int __must_check arch_phys_wc_index(int handle);
370 #define arch_phys_wc_index arch_phys_wc_index
371
372 extern int __must_check arch_phys_wc_add(unsigned long base,
373 unsigned long size);
374 extern void arch_phys_wc_del(int handle);
375 #define arch_phys_wc_add arch_phys_wc_add
376 #endif
377
378 #ifdef CONFIG_X86_PAT
379 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size);
380 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size);
381 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc
382 #endif
383
384 #endif /* _ASM_X86_IO_H */ 1
2 /*
3 * NXP (Philips) SCC+++(SCN+++) serial driver
4 *
5 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
6 *
7 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #define SUPPORT_SYSRQ
17 #endif
18
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial.h>
26 #include <linux/io.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/spinlock.h>
30 #include <linux/platform_device.h>
31 #include <linux/platform_data/serial-sccnxp.h>
32 #include <linux/regulator/consumer.h>
33
34 #define SCCNXP_NAME "uart-sccnxp"
35 #define SCCNXP_MAJOR 204
36 #define SCCNXP_MINOR 205
37
38 #define SCCNXP_MR_REG (0x00)
39 # define MR0_BAUD_NORMAL (0 << 0)
40 # define MR0_BAUD_EXT1 (1 << 0)
41 # define MR0_BAUD_EXT2 (5 << 0)
42 # define MR0_FIFO (1 << 3)
43 # define MR0_TXLVL (1 << 4)
44 # define MR1_BITS_5 (0 << 0)
45 # define MR1_BITS_6 (1 << 0)
46 # define MR1_BITS_7 (2 << 0)
47 # define MR1_BITS_8 (3 << 0)
48 # define MR1_PAR_EVN (0 << 2)
49 # define MR1_PAR_ODD (1 << 2)
50 # define MR1_PAR_NO (4 << 2)
51 # define MR2_STOP1 (7 << 0)
52 # define MR2_STOP2 (0xf << 0)
53 #define SCCNXP_SR_REG (0x01)
54 #define SCCNXP_CSR_REG SCCNXP_SR_REG
55 # define SR_RXRDY (1 << 0)
56 # define SR_FULL (1 << 1)
57 # define SR_TXRDY (1 << 2)
58 # define SR_TXEMT (1 << 3)
59 # define SR_OVR (1 << 4)
60 # define SR_PE (1 << 5)
61 # define SR_FE (1 << 6)
62 # define SR_BRK (1 << 7)
63 #define SCCNXP_CR_REG (0x02)
64 # define CR_RX_ENABLE (1 << 0)
65 # define CR_RX_DISABLE (1 << 1)
66 # define CR_TX_ENABLE (1 << 2)
67 # define CR_TX_DISABLE (1 << 3)
68 # define CR_CMD_MRPTR1 (0x01 << 4)
69 # define CR_CMD_RX_RESET (0x02 << 4)
70 # define CR_CMD_TX_RESET (0x03 << 4)
71 # define CR_CMD_STATUS_RESET (0x04 << 4)
72 # define CR_CMD_BREAK_RESET (0x05 << 4)
73 # define CR_CMD_START_BREAK (0x06 << 4)
74 # define CR_CMD_STOP_BREAK (0x07 << 4)
75 # define CR_CMD_MRPTR0 (0x0b << 4)
76 #define SCCNXP_RHR_REG (0x03)
77 #define SCCNXP_THR_REG SCCNXP_RHR_REG
78 #define SCCNXP_IPCR_REG (0x04)
79 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
80 # define ACR_BAUD0 (0 << 7)
81 # define ACR_BAUD1 (1 << 7)
82 # define ACR_TIMER_MODE (6 << 4)
83 #define SCCNXP_ISR_REG (0x05)
84 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
85 # define IMR_TXRDY (1 << 0)
86 # define IMR_RXRDY (1 << 1)
87 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
88 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
89 #define SCCNXP_IPR_REG (0x0d)
90 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
91 #define SCCNXP_SOP_REG (0x0e)
92 #define SCCNXP_ROP_REG (0x0f)
93
94 /* Route helpers */
95 #define MCTRL_MASK(sig) (0xf << (sig))
96 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
97 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
98
99 #define SCCNXP_HAVE_IO 0x00000001
100 #define SCCNXP_HAVE_MR0 0x00000002
101
102 struct sccnxp_chip {
103 const char *name;
104 unsigned int nr;
105 unsigned long freq_min;
106 unsigned long freq_std;
107 unsigned long freq_max;
108 unsigned int flags;
109 unsigned int fifosize;
110 };
111
112 struct sccnxp_port {
113 struct uart_driver uart;
114 struct uart_port port[SCCNXP_MAX_UARTS];
115 bool opened[SCCNXP_MAX_UARTS];
116
117 int irq;
118 u8 imr;
119
120 struct sccnxp_chip *chip;
121
122 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
123 struct console console;
124 #endif
125
126 spinlock_t lock;
127
128 bool poll;
129 struct timer_list timer;
130
131 struct sccnxp_pdata pdata;
132
133 struct regulator *regulator;
134 };
135
136 static const struct sccnxp_chip sc2681 = {
137 .name = "SC2681",
138 .nr = 2,
139 .freq_min = 1000000,
140 .freq_std = 3686400,
141 .freq_max = 4000000,
142 .flags = SCCNXP_HAVE_IO,
143 .fifosize = 3,
144 };
145
146 static const struct sccnxp_chip sc2691 = {
147 .name = "SC2691",
148 .nr = 1,
149 .freq_min = 1000000,
150 .freq_std = 3686400,
151 .freq_max = 4000000,
152 .flags = 0,
153 .fifosize = 3,
154 };
155
156 static const struct sccnxp_chip sc2692 = {
157 .name = "SC2692",
158 .nr = 2,
159 .freq_min = 1000000,
160 .freq_std = 3686400,
161 .freq_max = 4000000,
162 .flags = SCCNXP_HAVE_IO,
163 .fifosize = 3,
164 };
165
166 static const struct sccnxp_chip sc2891 = {
167 .name = "SC2891",
168 .nr = 1,
169 .freq_min = 100000,
170 .freq_std = 3686400,
171 .freq_max = 8000000,
172 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
173 .fifosize = 16,
174 };
175
176 static const struct sccnxp_chip sc2892 = {
177 .name = "SC2892",
178 .nr = 2,
179 .freq_min = 100000,
180 .freq_std = 3686400,
181 .freq_max = 8000000,
182 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
183 .fifosize = 16,
184 };
185
186 static const struct sccnxp_chip sc28202 = {
187 .name = "SC28202",
188 .nr = 2,
189 .freq_min = 1000000,
190 .freq_std = 14745600,
191 .freq_max = 50000000,
192 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
193 .fifosize = 256,
194 };
195
196 static const struct sccnxp_chip sc68681 = {
197 .name = "SC68681",
198 .nr = 2,
199 .freq_min = 1000000,
200 .freq_std = 3686400,
201 .freq_max = 4000000,
202 .flags = SCCNXP_HAVE_IO,
203 .fifosize = 3,
204 };
205
206 static const struct sccnxp_chip sc68692 = {
207 .name = "SC68692",
208 .nr = 2,
209 .freq_min = 1000000,
210 .freq_std = 3686400,
211 .freq_max = 4000000,
212 .flags = SCCNXP_HAVE_IO,
213 .fifosize = 3,
214 };
215
216 static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
217 {
218 return readb(port->membase + (reg << port->regshift));
219 }
220
221 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
222 {
223 writeb(v, port->membase + (reg << port->regshift));
224 }
225
226 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
227 {
228 return sccnxp_read(port, (port->line << 3) + reg);
229 }
230
231 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
232 {
233 sccnxp_write(port, (port->line << 3) + reg, v);
234 }
235
236 static int sccnxp_update_best_err(int a, int b, int *besterr)
237 {
238 int err = abs(a - b);
239
240 if ((*besterr < 0) || (*besterr > err)) {
241 *besterr = err;
242 return 0;
243 }
244
245 return 1;
246 }
247
248 static const struct {
249 u8 csr;
250 u8 acr;
251 u8 mr0;
252 int baud;
253 } baud_std[] = {
254 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
255 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
256 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
257 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
258 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
259 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
260 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
261 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
262 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
263 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
264 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
265 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
266 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
267 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
268 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
269 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
270 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
271 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
272 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
273 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
274 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
275 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
276 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
277 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
278 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
279 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
280 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
281 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
282 { 0, 0, 0, 0 }
283 };
284
285 static int sccnxp_set_baud(struct uart_port *port, int baud)
286 {
287 struct sccnxp_port *s = dev_get_drvdata(port->dev);
288 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
289 struct sccnxp_chip *chip = s->chip;
290 u8 i, acr = 0, csr = 0, mr0 = 0;
291
292 /* Find best baud from table */
293 for (i = 0; baud_std[i].baud && besterr; i++) {
294 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
295 continue;
296 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
297 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
298 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
299 acr = baud_std[i].acr;
300 csr = baud_std[i].csr;
301 mr0 = baud_std[i].mr0;
302 bestbaud = tmp_baud;
303 }
304 }
305
306 if (chip->flags & SCCNXP_HAVE_MR0) {
307 /* Enable FIFO, set half level for TX */
308 mr0 |= MR0_FIFO | MR0_TXLVL;
309 /* Update MR0 */
310 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
311 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
312 }
313
314 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
315 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
316
317 if (baud != bestbaud)
318 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
319 baud, bestbaud);
320
321 return bestbaud;
322 }
323
324 static void sccnxp_enable_irq(struct uart_port *port, int mask)
325 {
326 struct sccnxp_port *s = dev_get_drvdata(port->dev);
327
328 s->imr |= mask << (port->line * 4);
329 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
330 }
331
332 static void sccnxp_disable_irq(struct uart_port *port, int mask)
333 {
334 struct sccnxp_port *s = dev_get_drvdata(port->dev);
335
336 s->imr &= ~(mask << (port->line * 4));
337 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
338 }
339
340 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
341 {
342 u8 bitmask;
343 struct sccnxp_port *s = dev_get_drvdata(port->dev);
344
345 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
346 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
347 if (state)
348 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
349 else
350 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
351 }
352 }
353
354 static void sccnxp_handle_rx(struct uart_port *port)
355 {
356 u8 sr;
357 unsigned int ch, flag;
358
359 for (;;) {
360 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
361 if (!(sr & SR_RXRDY))
362 break;
363 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
364
365 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
366
367 port->icount.rx++;
368 flag = TTY_NORMAL;
369
370 if (unlikely(sr)) {
371 if (sr & SR_BRK) {
372 port->icount.brk++;
373 sccnxp_port_write(port, SCCNXP_CR_REG,
374 CR_CMD_BREAK_RESET);
375 if (uart_handle_break(port))
376 continue;
377 } else if (sr & SR_PE)
378 port->icount.parity++;
379 else if (sr & SR_FE)
380 port->icount.frame++;
381 else if (sr & SR_OVR) {
382 port->icount.overrun++;
383 sccnxp_port_write(port, SCCNXP_CR_REG,
384 CR_CMD_STATUS_RESET);
385 }
386
387 sr &= port->read_status_mask;
388 if (sr & SR_BRK)
389 flag = TTY_BREAK;
390 else if (sr & SR_PE)
391 flag = TTY_PARITY;
392 else if (sr & SR_FE)
393 flag = TTY_FRAME;
394 else if (sr & SR_OVR)
395 flag = TTY_OVERRUN;
396 }
397
398 if (uart_handle_sysrq_char(port, ch))
399 continue;
400
401 if (sr & port->ignore_status_mask)
402 continue;
403
404 uart_insert_char(port, sr, SR_OVR, ch, flag);
405 }
406
407 tty_flip_buffer_push(&port->state->port);
408 }
409
410 static void sccnxp_handle_tx(struct uart_port *port)
411 {
412 u8 sr;
413 struct circ_buf *xmit = &port->state->xmit;
414 struct sccnxp_port *s = dev_get_drvdata(port->dev);
415
416 if (unlikely(port->x_char)) {
417 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
418 port->icount.tx++;
419 port->x_char = 0;
420 return;
421 }
422
423 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
424 /* Disable TX if FIFO is empty */
425 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
426 sccnxp_disable_irq(port, IMR_TXRDY);
427
428 /* Set direction to input */
429 if (s->chip->flags & SCCNXP_HAVE_IO)
430 sccnxp_set_bit(port, DIR_OP, 0);
431 }
432 return;
433 }
434
435 while (!uart_circ_empty(xmit)) {
436 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
437 if (!(sr & SR_TXRDY))
438 break;
439
440 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
441 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
442 port->icount.tx++;
443 }
444
445 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
446 uart_write_wakeup(port);
447 }
448
449 static void sccnxp_handle_events(struct sccnxp_port *s)
450 {
451 int i;
452 u8 isr;
453
454 do {
455 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
456 isr &= s->imr;
457 if (!isr)
458 break;
459
460 for (i = 0; i < s->uart.nr; i++) {
461 if (s->opened[i] && (isr & ISR_RXRDY(i)))
462 sccnxp_handle_rx(&s->port[i]);
463 if (s->opened[i] && (isr & ISR_TXRDY(i)))
464 sccnxp_handle_tx(&s->port[i]);
465 }
466 } while (1);
467 }
468
469 static void sccnxp_timer(unsigned long data)
470 {
471 struct sccnxp_port *s = (struct sccnxp_port *)data;
472 unsigned long flags;
473
474 spin_lock_irqsave(&s->lock, flags);
475 sccnxp_handle_events(s);
476 spin_unlock_irqrestore(&s->lock, flags);
477
478 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
479 }
480
481 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
482 {
483 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
484 unsigned long flags;
485
486 spin_lock_irqsave(&s->lock, flags);
487 sccnxp_handle_events(s);
488 spin_unlock_irqrestore(&s->lock, flags);
489
490 return IRQ_HANDLED;
491 }
492
493 static void sccnxp_start_tx(struct uart_port *port)
494 {
495 struct sccnxp_port *s = dev_get_drvdata(port->dev);
496 unsigned long flags;
497
498 spin_lock_irqsave(&s->lock, flags);
499
500 /* Set direction to output */
501 if (s->chip->flags & SCCNXP_HAVE_IO)
502 sccnxp_set_bit(port, DIR_OP, 1);
503
504 sccnxp_enable_irq(port, IMR_TXRDY);
505
506 spin_unlock_irqrestore(&s->lock, flags);
507 }
508
509 static void sccnxp_stop_tx(struct uart_port *port)
510 {
511 /* Do nothing */
512 }
513
514 static void sccnxp_stop_rx(struct uart_port *port)
515 {
516 struct sccnxp_port *s = dev_get_drvdata(port->dev);
517 unsigned long flags;
518
519 spin_lock_irqsave(&s->lock, flags);
520 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
521 spin_unlock_irqrestore(&s->lock, flags);
522 }
523
524 static unsigned int sccnxp_tx_empty(struct uart_port *port)
525 {
526 u8 val;
527 unsigned long flags;
528 struct sccnxp_port *s = dev_get_drvdata(port->dev);
529
530 spin_lock_irqsave(&s->lock, flags);
531 val = sccnxp_port_read(port, SCCNXP_SR_REG);
532 spin_unlock_irqrestore(&s->lock, flags);
533
534 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
535 }
536
537 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
538 {
539 struct sccnxp_port *s = dev_get_drvdata(port->dev);
540 unsigned long flags;
541
542 if (!(s->chip->flags & SCCNXP_HAVE_IO))
543 return;
544
545 spin_lock_irqsave(&s->lock, flags);
546
547 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
548 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
549
550 spin_unlock_irqrestore(&s->lock, flags);
551 }
552
553 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
554 {
555 u8 bitmask, ipr;
556 unsigned long flags;
557 struct sccnxp_port *s = dev_get_drvdata(port->dev);
558 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
559
560 if (!(s->chip->flags & SCCNXP_HAVE_IO))
561 return mctrl;
562
563 spin_lock_irqsave(&s->lock, flags);
564
565 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
566
567 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
568 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
569 DSR_IP);
570 mctrl &= ~TIOCM_DSR;
571 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
572 }
573 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
574 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
575 CTS_IP);
576 mctrl &= ~TIOCM_CTS;
577 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
578 }
579 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
580 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
581 DCD_IP);
582 mctrl &= ~TIOCM_CAR;
583 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
584 }
585 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
586 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
587 RNG_IP);
588 mctrl &= ~TIOCM_RNG;
589 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
590 }
591
592 spin_unlock_irqrestore(&s->lock, flags);
593
594 return mctrl;
595 }
596
597 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
598 {
599 struct sccnxp_port *s = dev_get_drvdata(port->dev);
600 unsigned long flags;
601
602 spin_lock_irqsave(&s->lock, flags);
603 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
604 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
605 spin_unlock_irqrestore(&s->lock, flags);
606 }
607
608 static void sccnxp_set_termios(struct uart_port *port,
609 struct ktermios *termios, struct ktermios *old)
610 {
611 struct sccnxp_port *s = dev_get_drvdata(port->dev);
612 unsigned long flags;
613 u8 mr1, mr2;
614 int baud;
615
616 spin_lock_irqsave(&s->lock, flags);
617
618 /* Mask termios capabilities we don't support */
619 termios->c_cflag &= ~CMSPAR;
620
621 /* Disable RX & TX, reset break condition, status and FIFOs */
622 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
623 CR_RX_DISABLE | CR_TX_DISABLE);
624 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
625 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
626 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
627
628 /* Word size */
629 switch (termios->c_cflag & CSIZE) {
630 case CS5:
631 mr1 = MR1_BITS_5;
632 break;
633 case CS6:
634 mr1 = MR1_BITS_6;
635 break;
636 case CS7:
637 mr1 = MR1_BITS_7;
638 break;
639 case CS8:
640 default:
641 mr1 = MR1_BITS_8;
642 break;
643 }
644
645 /* Parity */
646 if (termios->c_cflag & PARENB) {
647 if (termios->c_cflag & PARODD)
648 mr1 |= MR1_PAR_ODD;
649 } else
650 mr1 |= MR1_PAR_NO;
651
652 /* Stop bits */
653 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
654
655 /* Update desired format */
656 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
657 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
658 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
659
660 /* Set read status mask */
661 port->read_status_mask = SR_OVR;
662 if (termios->c_iflag & INPCK)
663 port->read_status_mask |= SR_PE | SR_FE;
664 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
665 port->read_status_mask |= SR_BRK;
666
667 /* Set status ignore mask */
668 port->ignore_status_mask = 0;
669 if (termios->c_iflag & IGNBRK)
670 port->ignore_status_mask |= SR_BRK;
671 if (termios->c_iflag & IGNPAR)
672 port->ignore_status_mask |= SR_PE;
673 if (!(termios->c_cflag & CREAD))
674 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
675
676 /* Setup baudrate */
677 baud = uart_get_baud_rate(port, termios, old, 50,
678 (s->chip->flags & SCCNXP_HAVE_MR0) ?
679 230400 : 38400);
680 baud = sccnxp_set_baud(port, baud);
681
682 /* Update timeout according to new baud rate */
683 uart_update_timeout(port, termios->c_cflag, baud);
684
685 /* Report actual baudrate back to core */
686 if (tty_termios_baud_rate(termios))
687 tty_termios_encode_baud_rate(termios, baud, baud);
688
689 /* Enable RX & TX */
690 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
691
692 spin_unlock_irqrestore(&s->lock, flags);
693 }
694
695 static int sccnxp_startup(struct uart_port *port)
696 {
697 struct sccnxp_port *s = dev_get_drvdata(port->dev);
698 unsigned long flags;
699
700 spin_lock_irqsave(&s->lock, flags);
701
702 if (s->chip->flags & SCCNXP_HAVE_IO) {
703 /* Outputs are controlled manually */
704 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
705 }
706
707 /* Reset break condition, status and FIFOs */
708 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
709 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
710 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
711 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
712
713 /* Enable RX & TX */
714 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
715
716 /* Enable RX interrupt */
717 sccnxp_enable_irq(port, IMR_RXRDY);
718
719 s->opened[port->line] = 1;
720
721 spin_unlock_irqrestore(&s->lock, flags);
722
723 return 0;
724 }
725
726 static void sccnxp_shutdown(struct uart_port *port)
727 {
728 struct sccnxp_port *s = dev_get_drvdata(port->dev);
729 unsigned long flags;
730
731 spin_lock_irqsave(&s->lock, flags);
732
733 s->opened[port->line] = 0;
734
735 /* Disable interrupts */
736 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
737
738 /* Disable TX & RX */
739 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
740
741 /* Leave direction to input */
742 if (s->chip->flags & SCCNXP_HAVE_IO)
743 sccnxp_set_bit(port, DIR_OP, 0);
744
745 spin_unlock_irqrestore(&s->lock, flags);
746 }
747
748 static const char *sccnxp_type(struct uart_port *port)
749 {
750 struct sccnxp_port *s = dev_get_drvdata(port->dev);
751
752 return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
753 }
754
755 static void sccnxp_release_port(struct uart_port *port)
756 {
757 /* Do nothing */
758 }
759
760 static int sccnxp_request_port(struct uart_port *port)
761 {
762 /* Do nothing */
763 return 0;
764 }
765
766 static void sccnxp_config_port(struct uart_port *port, int flags)
767 {
768 if (flags & UART_CONFIG_TYPE)
769 port->type = PORT_SC26XX;
770 }
771
772 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
773 {
774 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
775 return 0;
776 if (s->irq == port->irq)
777 return 0;
778
779 return -EINVAL;
780 }
781
782 static const struct uart_ops sccnxp_ops = {
783 .tx_empty = sccnxp_tx_empty,
784 .set_mctrl = sccnxp_set_mctrl,
785 .get_mctrl = sccnxp_get_mctrl,
786 .stop_tx = sccnxp_stop_tx,
787 .start_tx = sccnxp_start_tx,
788 .stop_rx = sccnxp_stop_rx,
789 .break_ctl = sccnxp_break_ctl,
790 .startup = sccnxp_startup,
791 .shutdown = sccnxp_shutdown,
792 .set_termios = sccnxp_set_termios,
793 .type = sccnxp_type,
794 .release_port = sccnxp_release_port,
795 .request_port = sccnxp_request_port,
796 .config_port = sccnxp_config_port,
797 .verify_port = sccnxp_verify_port,
798 };
799
800 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
801 static void sccnxp_console_putchar(struct uart_port *port, int c)
802 {
803 int tryes = 100000;
804
805 while (tryes--) {
806 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
807 sccnxp_port_write(port, SCCNXP_THR_REG, c);
808 break;
809 }
810 barrier();
811 }
812 }
813
814 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
815 {
816 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
817 struct uart_port *port = &s->port[co->index];
818 unsigned long flags;
819
820 spin_lock_irqsave(&s->lock, flags);
821 uart_console_write(port, c, n, sccnxp_console_putchar);
822 spin_unlock_irqrestore(&s->lock, flags);
823 }
824
825 static int sccnxp_console_setup(struct console *co, char *options)
826 {
827 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
828 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
829 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
830
831 if (options)
832 uart_parse_options(options, &baud, &parity, &bits, &flow);
833
834 return uart_set_options(port, co, baud, parity, bits, flow);
835 }
836 #endif
837
838 static const struct platform_device_id sccnxp_id_table[] = {
839 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },
840 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },
841 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },
842 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },
843 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },
844 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, },
845 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, },
846 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, },
847 { }
848 };
849 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
850
851 static int sccnxp_probe(struct platform_device *pdev)
852 {
853 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
854 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
855 int i, ret, uartclk;
856 struct sccnxp_port *s;
857 void __iomem *membase;
858 struct clk *clk;
859
860 membase = devm_ioremap_resource(&pdev->dev, res);
861 if (IS_ERR(membase))
862 return PTR_ERR(membase);
863
864 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
865 if (!s) {
866 dev_err(&pdev->dev, "Error allocating port structure\n");
867 return -ENOMEM;
868 }
869 platform_set_drvdata(pdev, s);
870
871 spin_lock_init(&s->lock);
872
873 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
874
875 s->regulator = devm_regulator_get(&pdev->dev, "vcc");
876 if (!IS_ERR(s->regulator)) {
877 ret = regulator_enable(s->regulator);
878 if (ret) {
879 dev_err(&pdev->dev,
880 "Failed to enable regulator: %i\n", ret);
881 return ret;
882 }
883 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
884 return -EPROBE_DEFER;
885
886 clk = devm_clk_get(&pdev->dev, NULL);
887 if (IS_ERR(clk)) {
888 ret = PTR_ERR(clk);
889 if (ret == -EPROBE_DEFER)
890 goto err_out;
891 uartclk = 0;
892 } else {
893 clk_prepare_enable(clk);
894 uartclk = clk_get_rate(clk);
895 }
896
897 if (!uartclk) {
898 dev_notice(&pdev->dev, "Using default clock frequency\n");
899 uartclk = s->chip->freq_std;
900 }
901
902 /* Check input frequency */
903 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
904 dev_err(&pdev->dev, "Frequency out of bounds\n");
905 ret = -EINVAL;
906 goto err_out;
907 }
908
909 if (pdata)
910 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
911
912 if (s->pdata.poll_time_us) {
913 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
914 s->pdata.poll_time_us);
915 s->poll = 1;
916 }
917
918 if (!s->poll) {
919 s->irq = platform_get_irq(pdev, 0);
920 if (s->irq < 0) {
921 dev_err(&pdev->dev, "Missing irq resource data\n");
922 ret = -ENXIO;
923 goto err_out;
924 }
925 }
926
927 s->uart.owner = THIS_MODULE;
928 s->uart.dev_name = "ttySC";
929 s->uart.major = SCCNXP_MAJOR;
930 s->uart.minor = SCCNXP_MINOR;
931 s->uart.nr = s->chip->nr;
932 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
933 s->uart.cons = &s->console;
934 s->uart.cons->device = uart_console_device;
935 s->uart.cons->write = sccnxp_console_write;
936 s->uart.cons->setup = sccnxp_console_setup;
937 s->uart.cons->flags = CON_PRINTBUFFER;
938 s->uart.cons->index = -1;
939 s->uart.cons->data = s;
940 strcpy(s->uart.cons->name, "ttySC");
941 #endif
942 ret = uart_register_driver(&s->uart);
943 if (ret) {
944 dev_err(&pdev->dev, "Registering UART driver failed\n");
945 goto err_out;
946 }
947
948 for (i = 0; i < s->uart.nr; i++) {
949 s->port[i].line = i;
950 s->port[i].dev = &pdev->dev;
951 s->port[i].irq = s->irq;
952 s->port[i].type = PORT_SC26XX;
953 s->port[i].fifosize = s->chip->fifosize;
954 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
955 s->port[i].iotype = UPIO_MEM;
956 s->port[i].mapbase = res->start;
957 s->port[i].membase = membase;
958 s->port[i].regshift = s->pdata.reg_shift;
959 s->port[i].uartclk = uartclk;
960 s->port[i].ops = &sccnxp_ops;
961 uart_add_one_port(&s->uart, &s->port[i]);
962 /* Set direction to input */
963 if (s->chip->flags & SCCNXP_HAVE_IO)
964 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
965 }
966
967 /* Disable interrupts */
968 s->imr = 0;
969 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
970
971 if (!s->poll) {
972 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
973 sccnxp_ist,
974 IRQF_TRIGGER_FALLING |
975 IRQF_ONESHOT,
976 dev_name(&pdev->dev), s);
977 if (!ret)
978 return 0;
979
980 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
981 } else {
982 init_timer(&s->timer);
983 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s);
984 mod_timer(&s->timer, jiffies +
985 usecs_to_jiffies(s->pdata.poll_time_us));
986 return 0;
987 }
988
989 uart_unregister_driver(&s->uart);
990 err_out:
991 if (!IS_ERR(s->regulator))
992 return regulator_disable(s->regulator);
993
994 return ret;
995 }
996
997 static int sccnxp_remove(struct platform_device *pdev)
998 {
999 int i;
1000 struct sccnxp_port *s = platform_get_drvdata(pdev);
1001
1002 if (!s->poll)
1003 devm_free_irq(&pdev->dev, s->irq, s);
1004 else
1005 del_timer_sync(&s->timer);
1006
1007 for (i = 0; i < s->uart.nr; i++)
1008 uart_remove_one_port(&s->uart, &s->port[i]);
1009
1010 uart_unregister_driver(&s->uart);
1011
1012 if (!IS_ERR(s->regulator))
1013 return regulator_disable(s->regulator);
1014
1015 return 0;
1016 }
1017
1018 static struct platform_driver sccnxp_uart_driver = {
1019 .driver = {
1020 .name = SCCNXP_NAME,
1021 },
1022 .probe = sccnxp_probe,
1023 .remove = sccnxp_remove,
1024 .id_table = sccnxp_id_table,
1025 };
1026 module_platform_driver(sccnxp_uart_driver);
1027
1028 MODULE_LICENSE("GPL v2");
1029 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1030 MODULE_DESCRIPTION("SCCNXP serial driver");
1031
1032
1033
1034
1035
1036 /* LDV_COMMENT_BEGIN_MAIN */
1037 #ifdef LDV_MAIN0_sequence_infinite_withcheck_stateful
1038
1039 /*###########################################################################*/
1040
1041 /*############## Driver Environment Generator 0.2 output ####################*/
1042
1043 /*###########################################################################*/
1044
1045
1046
1047 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test if all kernel resources are correctly released by driver before driver will be unloaded. */
1048 void ldv_check_final_state(void);
1049
1050 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result. */
1051 void ldv_check_return_value(int res);
1052
1053 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result of probe() function. */
1054 void ldv_check_return_value_probe(int res);
1055
1056 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Initializes the model. */
1057 void ldv_initialize(void);
1058
1059 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Reinitializes the model between distinct model function calls. */
1060 void ldv_handler_precall(void);
1061
1062 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Returns arbitrary interger value. */
1063 int nondet_int(void);
1064
1065 /* LDV_COMMENT_VAR_DECLARE_LDV Special variable for LDV verifier. */
1066 int LDV_IN_INTERRUPT;
1067
1068 /* LDV_COMMENT_FUNCTION_MAIN Main function for LDV verifier. */
1069 void ldv_main0_sequence_infinite_withcheck_stateful(void) {
1070
1071
1072
1073 /* LDV_COMMENT_BEGIN_VARIABLE_DECLARATION_PART */
1074 /*============================= VARIABLE DECLARATION PART =============================*/
1075 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
1076 /* content: static unsigned int sccnxp_tx_empty(struct uart_port *port)*/
1077 /* LDV_COMMENT_BEGIN_PREP */
1078 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1079 #define SUPPORT_SYSRQ
1080 #endif
1081 #define SCCNXP_NAME "uart-sccnxp"
1082 #define SCCNXP_MAJOR 204
1083 #define SCCNXP_MINOR 205
1084 #define SCCNXP_MR_REG (0x00)
1085 # define MR0_BAUD_NORMAL (0 << 0)
1086 # define MR0_BAUD_EXT1 (1 << 0)
1087 # define MR0_BAUD_EXT2 (5 << 0)
1088 # define MR0_FIFO (1 << 3)
1089 # define MR0_TXLVL (1 << 4)
1090 # define MR1_BITS_5 (0 << 0)
1091 # define MR1_BITS_6 (1 << 0)
1092 # define MR1_BITS_7 (2 << 0)
1093 # define MR1_BITS_8 (3 << 0)
1094 # define MR1_PAR_EVN (0 << 2)
1095 # define MR1_PAR_ODD (1 << 2)
1096 # define MR1_PAR_NO (4 << 2)
1097 # define MR2_STOP1 (7 << 0)
1098 # define MR2_STOP2 (0xf << 0)
1099 #define SCCNXP_SR_REG (0x01)
1100 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1101 # define SR_RXRDY (1 << 0)
1102 # define SR_FULL (1 << 1)
1103 # define SR_TXRDY (1 << 2)
1104 # define SR_TXEMT (1 << 3)
1105 # define SR_OVR (1 << 4)
1106 # define SR_PE (1 << 5)
1107 # define SR_FE (1 << 6)
1108 # define SR_BRK (1 << 7)
1109 #define SCCNXP_CR_REG (0x02)
1110 # define CR_RX_ENABLE (1 << 0)
1111 # define CR_RX_DISABLE (1 << 1)
1112 # define CR_TX_ENABLE (1 << 2)
1113 # define CR_TX_DISABLE (1 << 3)
1114 # define CR_CMD_MRPTR1 (0x01 << 4)
1115 # define CR_CMD_RX_RESET (0x02 << 4)
1116 # define CR_CMD_TX_RESET (0x03 << 4)
1117 # define CR_CMD_STATUS_RESET (0x04 << 4)
1118 # define CR_CMD_BREAK_RESET (0x05 << 4)
1119 # define CR_CMD_START_BREAK (0x06 << 4)
1120 # define CR_CMD_STOP_BREAK (0x07 << 4)
1121 # define CR_CMD_MRPTR0 (0x0b << 4)
1122 #define SCCNXP_RHR_REG (0x03)
1123 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1124 #define SCCNXP_IPCR_REG (0x04)
1125 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1126 # define ACR_BAUD0 (0 << 7)
1127 # define ACR_BAUD1 (1 << 7)
1128 # define ACR_TIMER_MODE (6 << 4)
1129 #define SCCNXP_ISR_REG (0x05)
1130 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1131 # define IMR_TXRDY (1 << 0)
1132 # define IMR_RXRDY (1 << 1)
1133 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1134 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1135 #define SCCNXP_IPR_REG (0x0d)
1136 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1137 #define SCCNXP_SOP_REG (0x0e)
1138 #define SCCNXP_ROP_REG (0x0f)
1139 #define MCTRL_MASK(sig) (0xf << (sig))
1140 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1141 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1142 #define SCCNXP_HAVE_IO 0x00000001
1143 #define SCCNXP_HAVE_MR0 0x00000002
1144 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1145 #endif
1146 /* LDV_COMMENT_END_PREP */
1147 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_tx_empty" */
1148 struct uart_port * var_group1;
1149 /* LDV_COMMENT_BEGIN_PREP */
1150 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1151 #endif
1152 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1153 #endif
1154 /* LDV_COMMENT_END_PREP */
1155 /* content: static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)*/
1156 /* LDV_COMMENT_BEGIN_PREP */
1157 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1158 #define SUPPORT_SYSRQ
1159 #endif
1160 #define SCCNXP_NAME "uart-sccnxp"
1161 #define SCCNXP_MAJOR 204
1162 #define SCCNXP_MINOR 205
1163 #define SCCNXP_MR_REG (0x00)
1164 # define MR0_BAUD_NORMAL (0 << 0)
1165 # define MR0_BAUD_EXT1 (1 << 0)
1166 # define MR0_BAUD_EXT2 (5 << 0)
1167 # define MR0_FIFO (1 << 3)
1168 # define MR0_TXLVL (1 << 4)
1169 # define MR1_BITS_5 (0 << 0)
1170 # define MR1_BITS_6 (1 << 0)
1171 # define MR1_BITS_7 (2 << 0)
1172 # define MR1_BITS_8 (3 << 0)
1173 # define MR1_PAR_EVN (0 << 2)
1174 # define MR1_PAR_ODD (1 << 2)
1175 # define MR1_PAR_NO (4 << 2)
1176 # define MR2_STOP1 (7 << 0)
1177 # define MR2_STOP2 (0xf << 0)
1178 #define SCCNXP_SR_REG (0x01)
1179 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1180 # define SR_RXRDY (1 << 0)
1181 # define SR_FULL (1 << 1)
1182 # define SR_TXRDY (1 << 2)
1183 # define SR_TXEMT (1 << 3)
1184 # define SR_OVR (1 << 4)
1185 # define SR_PE (1 << 5)
1186 # define SR_FE (1 << 6)
1187 # define SR_BRK (1 << 7)
1188 #define SCCNXP_CR_REG (0x02)
1189 # define CR_RX_ENABLE (1 << 0)
1190 # define CR_RX_DISABLE (1 << 1)
1191 # define CR_TX_ENABLE (1 << 2)
1192 # define CR_TX_DISABLE (1 << 3)
1193 # define CR_CMD_MRPTR1 (0x01 << 4)
1194 # define CR_CMD_RX_RESET (0x02 << 4)
1195 # define CR_CMD_TX_RESET (0x03 << 4)
1196 # define CR_CMD_STATUS_RESET (0x04 << 4)
1197 # define CR_CMD_BREAK_RESET (0x05 << 4)
1198 # define CR_CMD_START_BREAK (0x06 << 4)
1199 # define CR_CMD_STOP_BREAK (0x07 << 4)
1200 # define CR_CMD_MRPTR0 (0x0b << 4)
1201 #define SCCNXP_RHR_REG (0x03)
1202 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1203 #define SCCNXP_IPCR_REG (0x04)
1204 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1205 # define ACR_BAUD0 (0 << 7)
1206 # define ACR_BAUD1 (1 << 7)
1207 # define ACR_TIMER_MODE (6 << 4)
1208 #define SCCNXP_ISR_REG (0x05)
1209 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1210 # define IMR_TXRDY (1 << 0)
1211 # define IMR_RXRDY (1 << 1)
1212 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1213 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1214 #define SCCNXP_IPR_REG (0x0d)
1215 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1216 #define SCCNXP_SOP_REG (0x0e)
1217 #define SCCNXP_ROP_REG (0x0f)
1218 #define MCTRL_MASK(sig) (0xf << (sig))
1219 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1220 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1221 #define SCCNXP_HAVE_IO 0x00000001
1222 #define SCCNXP_HAVE_MR0 0x00000002
1223 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1224 #endif
1225 /* LDV_COMMENT_END_PREP */
1226 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_mctrl" */
1227 unsigned int var_sccnxp_set_mctrl_18_p1;
1228 /* LDV_COMMENT_BEGIN_PREP */
1229 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1230 #endif
1231 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1232 #endif
1233 /* LDV_COMMENT_END_PREP */
1234 /* content: static unsigned int sccnxp_get_mctrl(struct uart_port *port)*/
1235 /* LDV_COMMENT_BEGIN_PREP */
1236 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1237 #define SUPPORT_SYSRQ
1238 #endif
1239 #define SCCNXP_NAME "uart-sccnxp"
1240 #define SCCNXP_MAJOR 204
1241 #define SCCNXP_MINOR 205
1242 #define SCCNXP_MR_REG (0x00)
1243 # define MR0_BAUD_NORMAL (0 << 0)
1244 # define MR0_BAUD_EXT1 (1 << 0)
1245 # define MR0_BAUD_EXT2 (5 << 0)
1246 # define MR0_FIFO (1 << 3)
1247 # define MR0_TXLVL (1 << 4)
1248 # define MR1_BITS_5 (0 << 0)
1249 # define MR1_BITS_6 (1 << 0)
1250 # define MR1_BITS_7 (2 << 0)
1251 # define MR1_BITS_8 (3 << 0)
1252 # define MR1_PAR_EVN (0 << 2)
1253 # define MR1_PAR_ODD (1 << 2)
1254 # define MR1_PAR_NO (4 << 2)
1255 # define MR2_STOP1 (7 << 0)
1256 # define MR2_STOP2 (0xf << 0)
1257 #define SCCNXP_SR_REG (0x01)
1258 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1259 # define SR_RXRDY (1 << 0)
1260 # define SR_FULL (1 << 1)
1261 # define SR_TXRDY (1 << 2)
1262 # define SR_TXEMT (1 << 3)
1263 # define SR_OVR (1 << 4)
1264 # define SR_PE (1 << 5)
1265 # define SR_FE (1 << 6)
1266 # define SR_BRK (1 << 7)
1267 #define SCCNXP_CR_REG (0x02)
1268 # define CR_RX_ENABLE (1 << 0)
1269 # define CR_RX_DISABLE (1 << 1)
1270 # define CR_TX_ENABLE (1 << 2)
1271 # define CR_TX_DISABLE (1 << 3)
1272 # define CR_CMD_MRPTR1 (0x01 << 4)
1273 # define CR_CMD_RX_RESET (0x02 << 4)
1274 # define CR_CMD_TX_RESET (0x03 << 4)
1275 # define CR_CMD_STATUS_RESET (0x04 << 4)
1276 # define CR_CMD_BREAK_RESET (0x05 << 4)
1277 # define CR_CMD_START_BREAK (0x06 << 4)
1278 # define CR_CMD_STOP_BREAK (0x07 << 4)
1279 # define CR_CMD_MRPTR0 (0x0b << 4)
1280 #define SCCNXP_RHR_REG (0x03)
1281 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1282 #define SCCNXP_IPCR_REG (0x04)
1283 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1284 # define ACR_BAUD0 (0 << 7)
1285 # define ACR_BAUD1 (1 << 7)
1286 # define ACR_TIMER_MODE (6 << 4)
1287 #define SCCNXP_ISR_REG (0x05)
1288 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1289 # define IMR_TXRDY (1 << 0)
1290 # define IMR_RXRDY (1 << 1)
1291 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1292 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1293 #define SCCNXP_IPR_REG (0x0d)
1294 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1295 #define SCCNXP_SOP_REG (0x0e)
1296 #define SCCNXP_ROP_REG (0x0f)
1297 #define MCTRL_MASK(sig) (0xf << (sig))
1298 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1299 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1300 #define SCCNXP_HAVE_IO 0x00000001
1301 #define SCCNXP_HAVE_MR0 0x00000002
1302 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1303 #endif
1304 /* LDV_COMMENT_END_PREP */
1305 /* LDV_COMMENT_BEGIN_PREP */
1306 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1307 #endif
1308 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1309 #endif
1310 /* LDV_COMMENT_END_PREP */
1311 /* content: static void sccnxp_stop_tx(struct uart_port *port)*/
1312 /* LDV_COMMENT_BEGIN_PREP */
1313 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1314 #define SUPPORT_SYSRQ
1315 #endif
1316 #define SCCNXP_NAME "uart-sccnxp"
1317 #define SCCNXP_MAJOR 204
1318 #define SCCNXP_MINOR 205
1319 #define SCCNXP_MR_REG (0x00)
1320 # define MR0_BAUD_NORMAL (0 << 0)
1321 # define MR0_BAUD_EXT1 (1 << 0)
1322 # define MR0_BAUD_EXT2 (5 << 0)
1323 # define MR0_FIFO (1 << 3)
1324 # define MR0_TXLVL (1 << 4)
1325 # define MR1_BITS_5 (0 << 0)
1326 # define MR1_BITS_6 (1 << 0)
1327 # define MR1_BITS_7 (2 << 0)
1328 # define MR1_BITS_8 (3 << 0)
1329 # define MR1_PAR_EVN (0 << 2)
1330 # define MR1_PAR_ODD (1 << 2)
1331 # define MR1_PAR_NO (4 << 2)
1332 # define MR2_STOP1 (7 << 0)
1333 # define MR2_STOP2 (0xf << 0)
1334 #define SCCNXP_SR_REG (0x01)
1335 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1336 # define SR_RXRDY (1 << 0)
1337 # define SR_FULL (1 << 1)
1338 # define SR_TXRDY (1 << 2)
1339 # define SR_TXEMT (1 << 3)
1340 # define SR_OVR (1 << 4)
1341 # define SR_PE (1 << 5)
1342 # define SR_FE (1 << 6)
1343 # define SR_BRK (1 << 7)
1344 #define SCCNXP_CR_REG (0x02)
1345 # define CR_RX_ENABLE (1 << 0)
1346 # define CR_RX_DISABLE (1 << 1)
1347 # define CR_TX_ENABLE (1 << 2)
1348 # define CR_TX_DISABLE (1 << 3)
1349 # define CR_CMD_MRPTR1 (0x01 << 4)
1350 # define CR_CMD_RX_RESET (0x02 << 4)
1351 # define CR_CMD_TX_RESET (0x03 << 4)
1352 # define CR_CMD_STATUS_RESET (0x04 << 4)
1353 # define CR_CMD_BREAK_RESET (0x05 << 4)
1354 # define CR_CMD_START_BREAK (0x06 << 4)
1355 # define CR_CMD_STOP_BREAK (0x07 << 4)
1356 # define CR_CMD_MRPTR0 (0x0b << 4)
1357 #define SCCNXP_RHR_REG (0x03)
1358 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1359 #define SCCNXP_IPCR_REG (0x04)
1360 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1361 # define ACR_BAUD0 (0 << 7)
1362 # define ACR_BAUD1 (1 << 7)
1363 # define ACR_TIMER_MODE (6 << 4)
1364 #define SCCNXP_ISR_REG (0x05)
1365 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1366 # define IMR_TXRDY (1 << 0)
1367 # define IMR_RXRDY (1 << 1)
1368 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1369 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1370 #define SCCNXP_IPR_REG (0x0d)
1371 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1372 #define SCCNXP_SOP_REG (0x0e)
1373 #define SCCNXP_ROP_REG (0x0f)
1374 #define MCTRL_MASK(sig) (0xf << (sig))
1375 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1376 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1377 #define SCCNXP_HAVE_IO 0x00000001
1378 #define SCCNXP_HAVE_MR0 0x00000002
1379 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1380 #endif
1381 /* LDV_COMMENT_END_PREP */
1382 /* LDV_COMMENT_BEGIN_PREP */
1383 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1384 #endif
1385 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1386 #endif
1387 /* LDV_COMMENT_END_PREP */
1388 /* content: static void sccnxp_start_tx(struct uart_port *port)*/
1389 /* LDV_COMMENT_BEGIN_PREP */
1390 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1391 #define SUPPORT_SYSRQ
1392 #endif
1393 #define SCCNXP_NAME "uart-sccnxp"
1394 #define SCCNXP_MAJOR 204
1395 #define SCCNXP_MINOR 205
1396 #define SCCNXP_MR_REG (0x00)
1397 # define MR0_BAUD_NORMAL (0 << 0)
1398 # define MR0_BAUD_EXT1 (1 << 0)
1399 # define MR0_BAUD_EXT2 (5 << 0)
1400 # define MR0_FIFO (1 << 3)
1401 # define MR0_TXLVL (1 << 4)
1402 # define MR1_BITS_5 (0 << 0)
1403 # define MR1_BITS_6 (1 << 0)
1404 # define MR1_BITS_7 (2 << 0)
1405 # define MR1_BITS_8 (3 << 0)
1406 # define MR1_PAR_EVN (0 << 2)
1407 # define MR1_PAR_ODD (1 << 2)
1408 # define MR1_PAR_NO (4 << 2)
1409 # define MR2_STOP1 (7 << 0)
1410 # define MR2_STOP2 (0xf << 0)
1411 #define SCCNXP_SR_REG (0x01)
1412 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1413 # define SR_RXRDY (1 << 0)
1414 # define SR_FULL (1 << 1)
1415 # define SR_TXRDY (1 << 2)
1416 # define SR_TXEMT (1 << 3)
1417 # define SR_OVR (1 << 4)
1418 # define SR_PE (1 << 5)
1419 # define SR_FE (1 << 6)
1420 # define SR_BRK (1 << 7)
1421 #define SCCNXP_CR_REG (0x02)
1422 # define CR_RX_ENABLE (1 << 0)
1423 # define CR_RX_DISABLE (1 << 1)
1424 # define CR_TX_ENABLE (1 << 2)
1425 # define CR_TX_DISABLE (1 << 3)
1426 # define CR_CMD_MRPTR1 (0x01 << 4)
1427 # define CR_CMD_RX_RESET (0x02 << 4)
1428 # define CR_CMD_TX_RESET (0x03 << 4)
1429 # define CR_CMD_STATUS_RESET (0x04 << 4)
1430 # define CR_CMD_BREAK_RESET (0x05 << 4)
1431 # define CR_CMD_START_BREAK (0x06 << 4)
1432 # define CR_CMD_STOP_BREAK (0x07 << 4)
1433 # define CR_CMD_MRPTR0 (0x0b << 4)
1434 #define SCCNXP_RHR_REG (0x03)
1435 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1436 #define SCCNXP_IPCR_REG (0x04)
1437 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1438 # define ACR_BAUD0 (0 << 7)
1439 # define ACR_BAUD1 (1 << 7)
1440 # define ACR_TIMER_MODE (6 << 4)
1441 #define SCCNXP_ISR_REG (0x05)
1442 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1443 # define IMR_TXRDY (1 << 0)
1444 # define IMR_RXRDY (1 << 1)
1445 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1446 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1447 #define SCCNXP_IPR_REG (0x0d)
1448 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1449 #define SCCNXP_SOP_REG (0x0e)
1450 #define SCCNXP_ROP_REG (0x0f)
1451 #define MCTRL_MASK(sig) (0xf << (sig))
1452 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1453 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1454 #define SCCNXP_HAVE_IO 0x00000001
1455 #define SCCNXP_HAVE_MR0 0x00000002
1456 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1457 #endif
1458 /* LDV_COMMENT_END_PREP */
1459 /* LDV_COMMENT_BEGIN_PREP */
1460 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1461 #endif
1462 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1463 #endif
1464 /* LDV_COMMENT_END_PREP */
1465 /* content: static void sccnxp_stop_rx(struct uart_port *port)*/
1466 /* LDV_COMMENT_BEGIN_PREP */
1467 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1468 #define SUPPORT_SYSRQ
1469 #endif
1470 #define SCCNXP_NAME "uart-sccnxp"
1471 #define SCCNXP_MAJOR 204
1472 #define SCCNXP_MINOR 205
1473 #define SCCNXP_MR_REG (0x00)
1474 # define MR0_BAUD_NORMAL (0 << 0)
1475 # define MR0_BAUD_EXT1 (1 << 0)
1476 # define MR0_BAUD_EXT2 (5 << 0)
1477 # define MR0_FIFO (1 << 3)
1478 # define MR0_TXLVL (1 << 4)
1479 # define MR1_BITS_5 (0 << 0)
1480 # define MR1_BITS_6 (1 << 0)
1481 # define MR1_BITS_7 (2 << 0)
1482 # define MR1_BITS_8 (3 << 0)
1483 # define MR1_PAR_EVN (0 << 2)
1484 # define MR1_PAR_ODD (1 << 2)
1485 # define MR1_PAR_NO (4 << 2)
1486 # define MR2_STOP1 (7 << 0)
1487 # define MR2_STOP2 (0xf << 0)
1488 #define SCCNXP_SR_REG (0x01)
1489 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1490 # define SR_RXRDY (1 << 0)
1491 # define SR_FULL (1 << 1)
1492 # define SR_TXRDY (1 << 2)
1493 # define SR_TXEMT (1 << 3)
1494 # define SR_OVR (1 << 4)
1495 # define SR_PE (1 << 5)
1496 # define SR_FE (1 << 6)
1497 # define SR_BRK (1 << 7)
1498 #define SCCNXP_CR_REG (0x02)
1499 # define CR_RX_ENABLE (1 << 0)
1500 # define CR_RX_DISABLE (1 << 1)
1501 # define CR_TX_ENABLE (1 << 2)
1502 # define CR_TX_DISABLE (1 << 3)
1503 # define CR_CMD_MRPTR1 (0x01 << 4)
1504 # define CR_CMD_RX_RESET (0x02 << 4)
1505 # define CR_CMD_TX_RESET (0x03 << 4)
1506 # define CR_CMD_STATUS_RESET (0x04 << 4)
1507 # define CR_CMD_BREAK_RESET (0x05 << 4)
1508 # define CR_CMD_START_BREAK (0x06 << 4)
1509 # define CR_CMD_STOP_BREAK (0x07 << 4)
1510 # define CR_CMD_MRPTR0 (0x0b << 4)
1511 #define SCCNXP_RHR_REG (0x03)
1512 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1513 #define SCCNXP_IPCR_REG (0x04)
1514 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1515 # define ACR_BAUD0 (0 << 7)
1516 # define ACR_BAUD1 (1 << 7)
1517 # define ACR_TIMER_MODE (6 << 4)
1518 #define SCCNXP_ISR_REG (0x05)
1519 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1520 # define IMR_TXRDY (1 << 0)
1521 # define IMR_RXRDY (1 << 1)
1522 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1523 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1524 #define SCCNXP_IPR_REG (0x0d)
1525 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1526 #define SCCNXP_SOP_REG (0x0e)
1527 #define SCCNXP_ROP_REG (0x0f)
1528 #define MCTRL_MASK(sig) (0xf << (sig))
1529 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1530 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1531 #define SCCNXP_HAVE_IO 0x00000001
1532 #define SCCNXP_HAVE_MR0 0x00000002
1533 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1534 #endif
1535 /* LDV_COMMENT_END_PREP */
1536 /* LDV_COMMENT_BEGIN_PREP */
1537 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1538 #endif
1539 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1540 #endif
1541 /* LDV_COMMENT_END_PREP */
1542 /* content: static void sccnxp_break_ctl(struct uart_port *port, int break_state)*/
1543 /* LDV_COMMENT_BEGIN_PREP */
1544 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1545 #define SUPPORT_SYSRQ
1546 #endif
1547 #define SCCNXP_NAME "uart-sccnxp"
1548 #define SCCNXP_MAJOR 204
1549 #define SCCNXP_MINOR 205
1550 #define SCCNXP_MR_REG (0x00)
1551 # define MR0_BAUD_NORMAL (0 << 0)
1552 # define MR0_BAUD_EXT1 (1 << 0)
1553 # define MR0_BAUD_EXT2 (5 << 0)
1554 # define MR0_FIFO (1 << 3)
1555 # define MR0_TXLVL (1 << 4)
1556 # define MR1_BITS_5 (0 << 0)
1557 # define MR1_BITS_6 (1 << 0)
1558 # define MR1_BITS_7 (2 << 0)
1559 # define MR1_BITS_8 (3 << 0)
1560 # define MR1_PAR_EVN (0 << 2)
1561 # define MR1_PAR_ODD (1 << 2)
1562 # define MR1_PAR_NO (4 << 2)
1563 # define MR2_STOP1 (7 << 0)
1564 # define MR2_STOP2 (0xf << 0)
1565 #define SCCNXP_SR_REG (0x01)
1566 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1567 # define SR_RXRDY (1 << 0)
1568 # define SR_FULL (1 << 1)
1569 # define SR_TXRDY (1 << 2)
1570 # define SR_TXEMT (1 << 3)
1571 # define SR_OVR (1 << 4)
1572 # define SR_PE (1 << 5)
1573 # define SR_FE (1 << 6)
1574 # define SR_BRK (1 << 7)
1575 #define SCCNXP_CR_REG (0x02)
1576 # define CR_RX_ENABLE (1 << 0)
1577 # define CR_RX_DISABLE (1 << 1)
1578 # define CR_TX_ENABLE (1 << 2)
1579 # define CR_TX_DISABLE (1 << 3)
1580 # define CR_CMD_MRPTR1 (0x01 << 4)
1581 # define CR_CMD_RX_RESET (0x02 << 4)
1582 # define CR_CMD_TX_RESET (0x03 << 4)
1583 # define CR_CMD_STATUS_RESET (0x04 << 4)
1584 # define CR_CMD_BREAK_RESET (0x05 << 4)
1585 # define CR_CMD_START_BREAK (0x06 << 4)
1586 # define CR_CMD_STOP_BREAK (0x07 << 4)
1587 # define CR_CMD_MRPTR0 (0x0b << 4)
1588 #define SCCNXP_RHR_REG (0x03)
1589 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1590 #define SCCNXP_IPCR_REG (0x04)
1591 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1592 # define ACR_BAUD0 (0 << 7)
1593 # define ACR_BAUD1 (1 << 7)
1594 # define ACR_TIMER_MODE (6 << 4)
1595 #define SCCNXP_ISR_REG (0x05)
1596 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1597 # define IMR_TXRDY (1 << 0)
1598 # define IMR_RXRDY (1 << 1)
1599 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1600 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1601 #define SCCNXP_IPR_REG (0x0d)
1602 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1603 #define SCCNXP_SOP_REG (0x0e)
1604 #define SCCNXP_ROP_REG (0x0f)
1605 #define MCTRL_MASK(sig) (0xf << (sig))
1606 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1607 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1608 #define SCCNXP_HAVE_IO 0x00000001
1609 #define SCCNXP_HAVE_MR0 0x00000002
1610 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1611 #endif
1612 /* LDV_COMMENT_END_PREP */
1613 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_break_ctl" */
1614 int var_sccnxp_break_ctl_20_p1;
1615 /* LDV_COMMENT_BEGIN_PREP */
1616 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1617 #endif
1618 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1619 #endif
1620 /* LDV_COMMENT_END_PREP */
1621 /* content: static int sccnxp_startup(struct uart_port *port)*/
1622 /* LDV_COMMENT_BEGIN_PREP */
1623 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1624 #define SUPPORT_SYSRQ
1625 #endif
1626 #define SCCNXP_NAME "uart-sccnxp"
1627 #define SCCNXP_MAJOR 204
1628 #define SCCNXP_MINOR 205
1629 #define SCCNXP_MR_REG (0x00)
1630 # define MR0_BAUD_NORMAL (0 << 0)
1631 # define MR0_BAUD_EXT1 (1 << 0)
1632 # define MR0_BAUD_EXT2 (5 << 0)
1633 # define MR0_FIFO (1 << 3)
1634 # define MR0_TXLVL (1 << 4)
1635 # define MR1_BITS_5 (0 << 0)
1636 # define MR1_BITS_6 (1 << 0)
1637 # define MR1_BITS_7 (2 << 0)
1638 # define MR1_BITS_8 (3 << 0)
1639 # define MR1_PAR_EVN (0 << 2)
1640 # define MR1_PAR_ODD (1 << 2)
1641 # define MR1_PAR_NO (4 << 2)
1642 # define MR2_STOP1 (7 << 0)
1643 # define MR2_STOP2 (0xf << 0)
1644 #define SCCNXP_SR_REG (0x01)
1645 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1646 # define SR_RXRDY (1 << 0)
1647 # define SR_FULL (1 << 1)
1648 # define SR_TXRDY (1 << 2)
1649 # define SR_TXEMT (1 << 3)
1650 # define SR_OVR (1 << 4)
1651 # define SR_PE (1 << 5)
1652 # define SR_FE (1 << 6)
1653 # define SR_BRK (1 << 7)
1654 #define SCCNXP_CR_REG (0x02)
1655 # define CR_RX_ENABLE (1 << 0)
1656 # define CR_RX_DISABLE (1 << 1)
1657 # define CR_TX_ENABLE (1 << 2)
1658 # define CR_TX_DISABLE (1 << 3)
1659 # define CR_CMD_MRPTR1 (0x01 << 4)
1660 # define CR_CMD_RX_RESET (0x02 << 4)
1661 # define CR_CMD_TX_RESET (0x03 << 4)
1662 # define CR_CMD_STATUS_RESET (0x04 << 4)
1663 # define CR_CMD_BREAK_RESET (0x05 << 4)
1664 # define CR_CMD_START_BREAK (0x06 << 4)
1665 # define CR_CMD_STOP_BREAK (0x07 << 4)
1666 # define CR_CMD_MRPTR0 (0x0b << 4)
1667 #define SCCNXP_RHR_REG (0x03)
1668 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1669 #define SCCNXP_IPCR_REG (0x04)
1670 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1671 # define ACR_BAUD0 (0 << 7)
1672 # define ACR_BAUD1 (1 << 7)
1673 # define ACR_TIMER_MODE (6 << 4)
1674 #define SCCNXP_ISR_REG (0x05)
1675 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1676 # define IMR_TXRDY (1 << 0)
1677 # define IMR_RXRDY (1 << 1)
1678 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1679 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1680 #define SCCNXP_IPR_REG (0x0d)
1681 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1682 #define SCCNXP_SOP_REG (0x0e)
1683 #define SCCNXP_ROP_REG (0x0f)
1684 #define MCTRL_MASK(sig) (0xf << (sig))
1685 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1686 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1687 #define SCCNXP_HAVE_IO 0x00000001
1688 #define SCCNXP_HAVE_MR0 0x00000002
1689 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1690 #endif
1691 /* LDV_COMMENT_END_PREP */
1692 /* LDV_COMMENT_BEGIN_PREP */
1693 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1694 #endif
1695 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1696 #endif
1697 /* LDV_COMMENT_END_PREP */
1698 /* content: static void sccnxp_shutdown(struct uart_port *port)*/
1699 /* LDV_COMMENT_BEGIN_PREP */
1700 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1701 #define SUPPORT_SYSRQ
1702 #endif
1703 #define SCCNXP_NAME "uart-sccnxp"
1704 #define SCCNXP_MAJOR 204
1705 #define SCCNXP_MINOR 205
1706 #define SCCNXP_MR_REG (0x00)
1707 # define MR0_BAUD_NORMAL (0 << 0)
1708 # define MR0_BAUD_EXT1 (1 << 0)
1709 # define MR0_BAUD_EXT2 (5 << 0)
1710 # define MR0_FIFO (1 << 3)
1711 # define MR0_TXLVL (1 << 4)
1712 # define MR1_BITS_5 (0 << 0)
1713 # define MR1_BITS_6 (1 << 0)
1714 # define MR1_BITS_7 (2 << 0)
1715 # define MR1_BITS_8 (3 << 0)
1716 # define MR1_PAR_EVN (0 << 2)
1717 # define MR1_PAR_ODD (1 << 2)
1718 # define MR1_PAR_NO (4 << 2)
1719 # define MR2_STOP1 (7 << 0)
1720 # define MR2_STOP2 (0xf << 0)
1721 #define SCCNXP_SR_REG (0x01)
1722 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1723 # define SR_RXRDY (1 << 0)
1724 # define SR_FULL (1 << 1)
1725 # define SR_TXRDY (1 << 2)
1726 # define SR_TXEMT (1 << 3)
1727 # define SR_OVR (1 << 4)
1728 # define SR_PE (1 << 5)
1729 # define SR_FE (1 << 6)
1730 # define SR_BRK (1 << 7)
1731 #define SCCNXP_CR_REG (0x02)
1732 # define CR_RX_ENABLE (1 << 0)
1733 # define CR_RX_DISABLE (1 << 1)
1734 # define CR_TX_ENABLE (1 << 2)
1735 # define CR_TX_DISABLE (1 << 3)
1736 # define CR_CMD_MRPTR1 (0x01 << 4)
1737 # define CR_CMD_RX_RESET (0x02 << 4)
1738 # define CR_CMD_TX_RESET (0x03 << 4)
1739 # define CR_CMD_STATUS_RESET (0x04 << 4)
1740 # define CR_CMD_BREAK_RESET (0x05 << 4)
1741 # define CR_CMD_START_BREAK (0x06 << 4)
1742 # define CR_CMD_STOP_BREAK (0x07 << 4)
1743 # define CR_CMD_MRPTR0 (0x0b << 4)
1744 #define SCCNXP_RHR_REG (0x03)
1745 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1746 #define SCCNXP_IPCR_REG (0x04)
1747 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1748 # define ACR_BAUD0 (0 << 7)
1749 # define ACR_BAUD1 (1 << 7)
1750 # define ACR_TIMER_MODE (6 << 4)
1751 #define SCCNXP_ISR_REG (0x05)
1752 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1753 # define IMR_TXRDY (1 << 0)
1754 # define IMR_RXRDY (1 << 1)
1755 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1756 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1757 #define SCCNXP_IPR_REG (0x0d)
1758 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1759 #define SCCNXP_SOP_REG (0x0e)
1760 #define SCCNXP_ROP_REG (0x0f)
1761 #define MCTRL_MASK(sig) (0xf << (sig))
1762 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1763 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1764 #define SCCNXP_HAVE_IO 0x00000001
1765 #define SCCNXP_HAVE_MR0 0x00000002
1766 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1767 #endif
1768 /* LDV_COMMENT_END_PREP */
1769 /* LDV_COMMENT_BEGIN_PREP */
1770 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1771 #endif
1772 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1773 #endif
1774 /* LDV_COMMENT_END_PREP */
1775 /* content: static void sccnxp_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)*/
1776 /* LDV_COMMENT_BEGIN_PREP */
1777 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1778 #define SUPPORT_SYSRQ
1779 #endif
1780 #define SCCNXP_NAME "uart-sccnxp"
1781 #define SCCNXP_MAJOR 204
1782 #define SCCNXP_MINOR 205
1783 #define SCCNXP_MR_REG (0x00)
1784 # define MR0_BAUD_NORMAL (0 << 0)
1785 # define MR0_BAUD_EXT1 (1 << 0)
1786 # define MR0_BAUD_EXT2 (5 << 0)
1787 # define MR0_FIFO (1 << 3)
1788 # define MR0_TXLVL (1 << 4)
1789 # define MR1_BITS_5 (0 << 0)
1790 # define MR1_BITS_6 (1 << 0)
1791 # define MR1_BITS_7 (2 << 0)
1792 # define MR1_BITS_8 (3 << 0)
1793 # define MR1_PAR_EVN (0 << 2)
1794 # define MR1_PAR_ODD (1 << 2)
1795 # define MR1_PAR_NO (4 << 2)
1796 # define MR2_STOP1 (7 << 0)
1797 # define MR2_STOP2 (0xf << 0)
1798 #define SCCNXP_SR_REG (0x01)
1799 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1800 # define SR_RXRDY (1 << 0)
1801 # define SR_FULL (1 << 1)
1802 # define SR_TXRDY (1 << 2)
1803 # define SR_TXEMT (1 << 3)
1804 # define SR_OVR (1 << 4)
1805 # define SR_PE (1 << 5)
1806 # define SR_FE (1 << 6)
1807 # define SR_BRK (1 << 7)
1808 #define SCCNXP_CR_REG (0x02)
1809 # define CR_RX_ENABLE (1 << 0)
1810 # define CR_RX_DISABLE (1 << 1)
1811 # define CR_TX_ENABLE (1 << 2)
1812 # define CR_TX_DISABLE (1 << 3)
1813 # define CR_CMD_MRPTR1 (0x01 << 4)
1814 # define CR_CMD_RX_RESET (0x02 << 4)
1815 # define CR_CMD_TX_RESET (0x03 << 4)
1816 # define CR_CMD_STATUS_RESET (0x04 << 4)
1817 # define CR_CMD_BREAK_RESET (0x05 << 4)
1818 # define CR_CMD_START_BREAK (0x06 << 4)
1819 # define CR_CMD_STOP_BREAK (0x07 << 4)
1820 # define CR_CMD_MRPTR0 (0x0b << 4)
1821 #define SCCNXP_RHR_REG (0x03)
1822 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1823 #define SCCNXP_IPCR_REG (0x04)
1824 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1825 # define ACR_BAUD0 (0 << 7)
1826 # define ACR_BAUD1 (1 << 7)
1827 # define ACR_TIMER_MODE (6 << 4)
1828 #define SCCNXP_ISR_REG (0x05)
1829 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1830 # define IMR_TXRDY (1 << 0)
1831 # define IMR_RXRDY (1 << 1)
1832 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1833 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1834 #define SCCNXP_IPR_REG (0x0d)
1835 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1836 #define SCCNXP_SOP_REG (0x0e)
1837 #define SCCNXP_ROP_REG (0x0f)
1838 #define MCTRL_MASK(sig) (0xf << (sig))
1839 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1840 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1841 #define SCCNXP_HAVE_IO 0x00000001
1842 #define SCCNXP_HAVE_MR0 0x00000002
1843 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1844 #endif
1845 /* LDV_COMMENT_END_PREP */
1846 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_termios" */
1847 struct ktermios * var_group2;
1848 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_termios" */
1849 struct ktermios * var_sccnxp_set_termios_21_p2;
1850 /* LDV_COMMENT_BEGIN_PREP */
1851 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1852 #endif
1853 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1854 #endif
1855 /* LDV_COMMENT_END_PREP */
1856 /* content: static const char *sccnxp_type(struct uart_port *port)*/
1857 /* LDV_COMMENT_BEGIN_PREP */
1858 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1859 #define SUPPORT_SYSRQ
1860 #endif
1861 #define SCCNXP_NAME "uart-sccnxp"
1862 #define SCCNXP_MAJOR 204
1863 #define SCCNXP_MINOR 205
1864 #define SCCNXP_MR_REG (0x00)
1865 # define MR0_BAUD_NORMAL (0 << 0)
1866 # define MR0_BAUD_EXT1 (1 << 0)
1867 # define MR0_BAUD_EXT2 (5 << 0)
1868 # define MR0_FIFO (1 << 3)
1869 # define MR0_TXLVL (1 << 4)
1870 # define MR1_BITS_5 (0 << 0)
1871 # define MR1_BITS_6 (1 << 0)
1872 # define MR1_BITS_7 (2 << 0)
1873 # define MR1_BITS_8 (3 << 0)
1874 # define MR1_PAR_EVN (0 << 2)
1875 # define MR1_PAR_ODD (1 << 2)
1876 # define MR1_PAR_NO (4 << 2)
1877 # define MR2_STOP1 (7 << 0)
1878 # define MR2_STOP2 (0xf << 0)
1879 #define SCCNXP_SR_REG (0x01)
1880 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1881 # define SR_RXRDY (1 << 0)
1882 # define SR_FULL (1 << 1)
1883 # define SR_TXRDY (1 << 2)
1884 # define SR_TXEMT (1 << 3)
1885 # define SR_OVR (1 << 4)
1886 # define SR_PE (1 << 5)
1887 # define SR_FE (1 << 6)
1888 # define SR_BRK (1 << 7)
1889 #define SCCNXP_CR_REG (0x02)
1890 # define CR_RX_ENABLE (1 << 0)
1891 # define CR_RX_DISABLE (1 << 1)
1892 # define CR_TX_ENABLE (1 << 2)
1893 # define CR_TX_DISABLE (1 << 3)
1894 # define CR_CMD_MRPTR1 (0x01 << 4)
1895 # define CR_CMD_RX_RESET (0x02 << 4)
1896 # define CR_CMD_TX_RESET (0x03 << 4)
1897 # define CR_CMD_STATUS_RESET (0x04 << 4)
1898 # define CR_CMD_BREAK_RESET (0x05 << 4)
1899 # define CR_CMD_START_BREAK (0x06 << 4)
1900 # define CR_CMD_STOP_BREAK (0x07 << 4)
1901 # define CR_CMD_MRPTR0 (0x0b << 4)
1902 #define SCCNXP_RHR_REG (0x03)
1903 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1904 #define SCCNXP_IPCR_REG (0x04)
1905 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1906 # define ACR_BAUD0 (0 << 7)
1907 # define ACR_BAUD1 (1 << 7)
1908 # define ACR_TIMER_MODE (6 << 4)
1909 #define SCCNXP_ISR_REG (0x05)
1910 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1911 # define IMR_TXRDY (1 << 0)
1912 # define IMR_RXRDY (1 << 1)
1913 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1914 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1915 #define SCCNXP_IPR_REG (0x0d)
1916 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1917 #define SCCNXP_SOP_REG (0x0e)
1918 #define SCCNXP_ROP_REG (0x0f)
1919 #define MCTRL_MASK(sig) (0xf << (sig))
1920 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1921 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1922 #define SCCNXP_HAVE_IO 0x00000001
1923 #define SCCNXP_HAVE_MR0 0x00000002
1924 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1925 #endif
1926 /* LDV_COMMENT_END_PREP */
1927 /* LDV_COMMENT_BEGIN_PREP */
1928 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1929 #endif
1930 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1931 #endif
1932 /* LDV_COMMENT_END_PREP */
1933 /* content: static void sccnxp_release_port(struct uart_port *port)*/
1934 /* LDV_COMMENT_BEGIN_PREP */
1935 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1936 #define SUPPORT_SYSRQ
1937 #endif
1938 #define SCCNXP_NAME "uart-sccnxp"
1939 #define SCCNXP_MAJOR 204
1940 #define SCCNXP_MINOR 205
1941 #define SCCNXP_MR_REG (0x00)
1942 # define MR0_BAUD_NORMAL (0 << 0)
1943 # define MR0_BAUD_EXT1 (1 << 0)
1944 # define MR0_BAUD_EXT2 (5 << 0)
1945 # define MR0_FIFO (1 << 3)
1946 # define MR0_TXLVL (1 << 4)
1947 # define MR1_BITS_5 (0 << 0)
1948 # define MR1_BITS_6 (1 << 0)
1949 # define MR1_BITS_7 (2 << 0)
1950 # define MR1_BITS_8 (3 << 0)
1951 # define MR1_PAR_EVN (0 << 2)
1952 # define MR1_PAR_ODD (1 << 2)
1953 # define MR1_PAR_NO (4 << 2)
1954 # define MR2_STOP1 (7 << 0)
1955 # define MR2_STOP2 (0xf << 0)
1956 #define SCCNXP_SR_REG (0x01)
1957 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1958 # define SR_RXRDY (1 << 0)
1959 # define SR_FULL (1 << 1)
1960 # define SR_TXRDY (1 << 2)
1961 # define SR_TXEMT (1 << 3)
1962 # define SR_OVR (1 << 4)
1963 # define SR_PE (1 << 5)
1964 # define SR_FE (1 << 6)
1965 # define SR_BRK (1 << 7)
1966 #define SCCNXP_CR_REG (0x02)
1967 # define CR_RX_ENABLE (1 << 0)
1968 # define CR_RX_DISABLE (1 << 1)
1969 # define CR_TX_ENABLE (1 << 2)
1970 # define CR_TX_DISABLE (1 << 3)
1971 # define CR_CMD_MRPTR1 (0x01 << 4)
1972 # define CR_CMD_RX_RESET (0x02 << 4)
1973 # define CR_CMD_TX_RESET (0x03 << 4)
1974 # define CR_CMD_STATUS_RESET (0x04 << 4)
1975 # define CR_CMD_BREAK_RESET (0x05 << 4)
1976 # define CR_CMD_START_BREAK (0x06 << 4)
1977 # define CR_CMD_STOP_BREAK (0x07 << 4)
1978 # define CR_CMD_MRPTR0 (0x0b << 4)
1979 #define SCCNXP_RHR_REG (0x03)
1980 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1981 #define SCCNXP_IPCR_REG (0x04)
1982 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1983 # define ACR_BAUD0 (0 << 7)
1984 # define ACR_BAUD1 (1 << 7)
1985 # define ACR_TIMER_MODE (6 << 4)
1986 #define SCCNXP_ISR_REG (0x05)
1987 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1988 # define IMR_TXRDY (1 << 0)
1989 # define IMR_RXRDY (1 << 1)
1990 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1991 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1992 #define SCCNXP_IPR_REG (0x0d)
1993 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1994 #define SCCNXP_SOP_REG (0x0e)
1995 #define SCCNXP_ROP_REG (0x0f)
1996 #define MCTRL_MASK(sig) (0xf << (sig))
1997 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1998 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1999 #define SCCNXP_HAVE_IO 0x00000001
2000 #define SCCNXP_HAVE_MR0 0x00000002
2001 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2002 #endif
2003 /* LDV_COMMENT_END_PREP */
2004 /* LDV_COMMENT_BEGIN_PREP */
2005 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2006 #endif
2007 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2008 #endif
2009 /* LDV_COMMENT_END_PREP */
2010 /* content: static int sccnxp_request_port(struct uart_port *port)*/
2011 /* LDV_COMMENT_BEGIN_PREP */
2012 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2013 #define SUPPORT_SYSRQ
2014 #endif
2015 #define SCCNXP_NAME "uart-sccnxp"
2016 #define SCCNXP_MAJOR 204
2017 #define SCCNXP_MINOR 205
2018 #define SCCNXP_MR_REG (0x00)
2019 # define MR0_BAUD_NORMAL (0 << 0)
2020 # define MR0_BAUD_EXT1 (1 << 0)
2021 # define MR0_BAUD_EXT2 (5 << 0)
2022 # define MR0_FIFO (1 << 3)
2023 # define MR0_TXLVL (1 << 4)
2024 # define MR1_BITS_5 (0 << 0)
2025 # define MR1_BITS_6 (1 << 0)
2026 # define MR1_BITS_7 (2 << 0)
2027 # define MR1_BITS_8 (3 << 0)
2028 # define MR1_PAR_EVN (0 << 2)
2029 # define MR1_PAR_ODD (1 << 2)
2030 # define MR1_PAR_NO (4 << 2)
2031 # define MR2_STOP1 (7 << 0)
2032 # define MR2_STOP2 (0xf << 0)
2033 #define SCCNXP_SR_REG (0x01)
2034 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2035 # define SR_RXRDY (1 << 0)
2036 # define SR_FULL (1 << 1)
2037 # define SR_TXRDY (1 << 2)
2038 # define SR_TXEMT (1 << 3)
2039 # define SR_OVR (1 << 4)
2040 # define SR_PE (1 << 5)
2041 # define SR_FE (1 << 6)
2042 # define SR_BRK (1 << 7)
2043 #define SCCNXP_CR_REG (0x02)
2044 # define CR_RX_ENABLE (1 << 0)
2045 # define CR_RX_DISABLE (1 << 1)
2046 # define CR_TX_ENABLE (1 << 2)
2047 # define CR_TX_DISABLE (1 << 3)
2048 # define CR_CMD_MRPTR1 (0x01 << 4)
2049 # define CR_CMD_RX_RESET (0x02 << 4)
2050 # define CR_CMD_TX_RESET (0x03 << 4)
2051 # define CR_CMD_STATUS_RESET (0x04 << 4)
2052 # define CR_CMD_BREAK_RESET (0x05 << 4)
2053 # define CR_CMD_START_BREAK (0x06 << 4)
2054 # define CR_CMD_STOP_BREAK (0x07 << 4)
2055 # define CR_CMD_MRPTR0 (0x0b << 4)
2056 #define SCCNXP_RHR_REG (0x03)
2057 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2058 #define SCCNXP_IPCR_REG (0x04)
2059 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2060 # define ACR_BAUD0 (0 << 7)
2061 # define ACR_BAUD1 (1 << 7)
2062 # define ACR_TIMER_MODE (6 << 4)
2063 #define SCCNXP_ISR_REG (0x05)
2064 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2065 # define IMR_TXRDY (1 << 0)
2066 # define IMR_RXRDY (1 << 1)
2067 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2068 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2069 #define SCCNXP_IPR_REG (0x0d)
2070 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2071 #define SCCNXP_SOP_REG (0x0e)
2072 #define SCCNXP_ROP_REG (0x0f)
2073 #define MCTRL_MASK(sig) (0xf << (sig))
2074 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2075 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2076 #define SCCNXP_HAVE_IO 0x00000001
2077 #define SCCNXP_HAVE_MR0 0x00000002
2078 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2079 #endif
2080 /* LDV_COMMENT_END_PREP */
2081 /* LDV_COMMENT_BEGIN_PREP */
2082 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2083 #endif
2084 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2085 #endif
2086 /* LDV_COMMENT_END_PREP */
2087 /* content: static void sccnxp_config_port(struct uart_port *port, int flags)*/
2088 /* LDV_COMMENT_BEGIN_PREP */
2089 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2090 #define SUPPORT_SYSRQ
2091 #endif
2092 #define SCCNXP_NAME "uart-sccnxp"
2093 #define SCCNXP_MAJOR 204
2094 #define SCCNXP_MINOR 205
2095 #define SCCNXP_MR_REG (0x00)
2096 # define MR0_BAUD_NORMAL (0 << 0)
2097 # define MR0_BAUD_EXT1 (1 << 0)
2098 # define MR0_BAUD_EXT2 (5 << 0)
2099 # define MR0_FIFO (1 << 3)
2100 # define MR0_TXLVL (1 << 4)
2101 # define MR1_BITS_5 (0 << 0)
2102 # define MR1_BITS_6 (1 << 0)
2103 # define MR1_BITS_7 (2 << 0)
2104 # define MR1_BITS_8 (3 << 0)
2105 # define MR1_PAR_EVN (0 << 2)
2106 # define MR1_PAR_ODD (1 << 2)
2107 # define MR1_PAR_NO (4 << 2)
2108 # define MR2_STOP1 (7 << 0)
2109 # define MR2_STOP2 (0xf << 0)
2110 #define SCCNXP_SR_REG (0x01)
2111 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2112 # define SR_RXRDY (1 << 0)
2113 # define SR_FULL (1 << 1)
2114 # define SR_TXRDY (1 << 2)
2115 # define SR_TXEMT (1 << 3)
2116 # define SR_OVR (1 << 4)
2117 # define SR_PE (1 << 5)
2118 # define SR_FE (1 << 6)
2119 # define SR_BRK (1 << 7)
2120 #define SCCNXP_CR_REG (0x02)
2121 # define CR_RX_ENABLE (1 << 0)
2122 # define CR_RX_DISABLE (1 << 1)
2123 # define CR_TX_ENABLE (1 << 2)
2124 # define CR_TX_DISABLE (1 << 3)
2125 # define CR_CMD_MRPTR1 (0x01 << 4)
2126 # define CR_CMD_RX_RESET (0x02 << 4)
2127 # define CR_CMD_TX_RESET (0x03 << 4)
2128 # define CR_CMD_STATUS_RESET (0x04 << 4)
2129 # define CR_CMD_BREAK_RESET (0x05 << 4)
2130 # define CR_CMD_START_BREAK (0x06 << 4)
2131 # define CR_CMD_STOP_BREAK (0x07 << 4)
2132 # define CR_CMD_MRPTR0 (0x0b << 4)
2133 #define SCCNXP_RHR_REG (0x03)
2134 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2135 #define SCCNXP_IPCR_REG (0x04)
2136 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2137 # define ACR_BAUD0 (0 << 7)
2138 # define ACR_BAUD1 (1 << 7)
2139 # define ACR_TIMER_MODE (6 << 4)
2140 #define SCCNXP_ISR_REG (0x05)
2141 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2142 # define IMR_TXRDY (1 << 0)
2143 # define IMR_RXRDY (1 << 1)
2144 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2145 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2146 #define SCCNXP_IPR_REG (0x0d)
2147 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2148 #define SCCNXP_SOP_REG (0x0e)
2149 #define SCCNXP_ROP_REG (0x0f)
2150 #define MCTRL_MASK(sig) (0xf << (sig))
2151 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2152 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2153 #define SCCNXP_HAVE_IO 0x00000001
2154 #define SCCNXP_HAVE_MR0 0x00000002
2155 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2156 #endif
2157 /* LDV_COMMENT_END_PREP */
2158 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_config_port" */
2159 int var_sccnxp_config_port_27_p1;
2160 /* LDV_COMMENT_BEGIN_PREP */
2161 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2162 #endif
2163 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2164 #endif
2165 /* LDV_COMMENT_END_PREP */
2166 /* content: static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)*/
2167 /* LDV_COMMENT_BEGIN_PREP */
2168 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2169 #define SUPPORT_SYSRQ
2170 #endif
2171 #define SCCNXP_NAME "uart-sccnxp"
2172 #define SCCNXP_MAJOR 204
2173 #define SCCNXP_MINOR 205
2174 #define SCCNXP_MR_REG (0x00)
2175 # define MR0_BAUD_NORMAL (0 << 0)
2176 # define MR0_BAUD_EXT1 (1 << 0)
2177 # define MR0_BAUD_EXT2 (5 << 0)
2178 # define MR0_FIFO (1 << 3)
2179 # define MR0_TXLVL (1 << 4)
2180 # define MR1_BITS_5 (0 << 0)
2181 # define MR1_BITS_6 (1 << 0)
2182 # define MR1_BITS_7 (2 << 0)
2183 # define MR1_BITS_8 (3 << 0)
2184 # define MR1_PAR_EVN (0 << 2)
2185 # define MR1_PAR_ODD (1 << 2)
2186 # define MR1_PAR_NO (4 << 2)
2187 # define MR2_STOP1 (7 << 0)
2188 # define MR2_STOP2 (0xf << 0)
2189 #define SCCNXP_SR_REG (0x01)
2190 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2191 # define SR_RXRDY (1 << 0)
2192 # define SR_FULL (1 << 1)
2193 # define SR_TXRDY (1 << 2)
2194 # define SR_TXEMT (1 << 3)
2195 # define SR_OVR (1 << 4)
2196 # define SR_PE (1 << 5)
2197 # define SR_FE (1 << 6)
2198 # define SR_BRK (1 << 7)
2199 #define SCCNXP_CR_REG (0x02)
2200 # define CR_RX_ENABLE (1 << 0)
2201 # define CR_RX_DISABLE (1 << 1)
2202 # define CR_TX_ENABLE (1 << 2)
2203 # define CR_TX_DISABLE (1 << 3)
2204 # define CR_CMD_MRPTR1 (0x01 << 4)
2205 # define CR_CMD_RX_RESET (0x02 << 4)
2206 # define CR_CMD_TX_RESET (0x03 << 4)
2207 # define CR_CMD_STATUS_RESET (0x04 << 4)
2208 # define CR_CMD_BREAK_RESET (0x05 << 4)
2209 # define CR_CMD_START_BREAK (0x06 << 4)
2210 # define CR_CMD_STOP_BREAK (0x07 << 4)
2211 # define CR_CMD_MRPTR0 (0x0b << 4)
2212 #define SCCNXP_RHR_REG (0x03)
2213 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2214 #define SCCNXP_IPCR_REG (0x04)
2215 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2216 # define ACR_BAUD0 (0 << 7)
2217 # define ACR_BAUD1 (1 << 7)
2218 # define ACR_TIMER_MODE (6 << 4)
2219 #define SCCNXP_ISR_REG (0x05)
2220 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2221 # define IMR_TXRDY (1 << 0)
2222 # define IMR_RXRDY (1 << 1)
2223 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2224 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2225 #define SCCNXP_IPR_REG (0x0d)
2226 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2227 #define SCCNXP_SOP_REG (0x0e)
2228 #define SCCNXP_ROP_REG (0x0f)
2229 #define MCTRL_MASK(sig) (0xf << (sig))
2230 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2231 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2232 #define SCCNXP_HAVE_IO 0x00000001
2233 #define SCCNXP_HAVE_MR0 0x00000002
2234 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2235 #endif
2236 /* LDV_COMMENT_END_PREP */
2237 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_verify_port" */
2238 struct serial_struct * var_group3;
2239 /* LDV_COMMENT_BEGIN_PREP */
2240 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2241 #endif
2242 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2243 #endif
2244 /* LDV_COMMENT_END_PREP */
2245
2246 /** STRUCT: struct type: platform_driver, struct name: sccnxp_uart_driver **/
2247 /* content: static int sccnxp_probe(struct platform_device *pdev)*/
2248 /* LDV_COMMENT_BEGIN_PREP */
2249 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2250 #define SUPPORT_SYSRQ
2251 #endif
2252 #define SCCNXP_NAME "uart-sccnxp"
2253 #define SCCNXP_MAJOR 204
2254 #define SCCNXP_MINOR 205
2255 #define SCCNXP_MR_REG (0x00)
2256 # define MR0_BAUD_NORMAL (0 << 0)
2257 # define MR0_BAUD_EXT1 (1 << 0)
2258 # define MR0_BAUD_EXT2 (5 << 0)
2259 # define MR0_FIFO (1 << 3)
2260 # define MR0_TXLVL (1 << 4)
2261 # define MR1_BITS_5 (0 << 0)
2262 # define MR1_BITS_6 (1 << 0)
2263 # define MR1_BITS_7 (2 << 0)
2264 # define MR1_BITS_8 (3 << 0)
2265 # define MR1_PAR_EVN (0 << 2)
2266 # define MR1_PAR_ODD (1 << 2)
2267 # define MR1_PAR_NO (4 << 2)
2268 # define MR2_STOP1 (7 << 0)
2269 # define MR2_STOP2 (0xf << 0)
2270 #define SCCNXP_SR_REG (0x01)
2271 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2272 # define SR_RXRDY (1 << 0)
2273 # define SR_FULL (1 << 1)
2274 # define SR_TXRDY (1 << 2)
2275 # define SR_TXEMT (1 << 3)
2276 # define SR_OVR (1 << 4)
2277 # define SR_PE (1 << 5)
2278 # define SR_FE (1 << 6)
2279 # define SR_BRK (1 << 7)
2280 #define SCCNXP_CR_REG (0x02)
2281 # define CR_RX_ENABLE (1 << 0)
2282 # define CR_RX_DISABLE (1 << 1)
2283 # define CR_TX_ENABLE (1 << 2)
2284 # define CR_TX_DISABLE (1 << 3)
2285 # define CR_CMD_MRPTR1 (0x01 << 4)
2286 # define CR_CMD_RX_RESET (0x02 << 4)
2287 # define CR_CMD_TX_RESET (0x03 << 4)
2288 # define CR_CMD_STATUS_RESET (0x04 << 4)
2289 # define CR_CMD_BREAK_RESET (0x05 << 4)
2290 # define CR_CMD_START_BREAK (0x06 << 4)
2291 # define CR_CMD_STOP_BREAK (0x07 << 4)
2292 # define CR_CMD_MRPTR0 (0x0b << 4)
2293 #define SCCNXP_RHR_REG (0x03)
2294 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2295 #define SCCNXP_IPCR_REG (0x04)
2296 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2297 # define ACR_BAUD0 (0 << 7)
2298 # define ACR_BAUD1 (1 << 7)
2299 # define ACR_TIMER_MODE (6 << 4)
2300 #define SCCNXP_ISR_REG (0x05)
2301 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2302 # define IMR_TXRDY (1 << 0)
2303 # define IMR_RXRDY (1 << 1)
2304 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2305 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2306 #define SCCNXP_IPR_REG (0x0d)
2307 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2308 #define SCCNXP_SOP_REG (0x0e)
2309 #define SCCNXP_ROP_REG (0x0f)
2310 #define MCTRL_MASK(sig) (0xf << (sig))
2311 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2312 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2313 #define SCCNXP_HAVE_IO 0x00000001
2314 #define SCCNXP_HAVE_MR0 0x00000002
2315 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2316 #endif
2317 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2318 #endif
2319 /* LDV_COMMENT_END_PREP */
2320 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_probe" */
2321 struct platform_device * var_group4;
2322 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "sccnxp_probe" */
2323 static int res_sccnxp_probe_32;
2324 /* content: static int sccnxp_remove(struct platform_device *pdev)*/
2325 /* LDV_COMMENT_BEGIN_PREP */
2326 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2327 #define SUPPORT_SYSRQ
2328 #endif
2329 #define SCCNXP_NAME "uart-sccnxp"
2330 #define SCCNXP_MAJOR 204
2331 #define SCCNXP_MINOR 205
2332 #define SCCNXP_MR_REG (0x00)
2333 # define MR0_BAUD_NORMAL (0 << 0)
2334 # define MR0_BAUD_EXT1 (1 << 0)
2335 # define MR0_BAUD_EXT2 (5 << 0)
2336 # define MR0_FIFO (1 << 3)
2337 # define MR0_TXLVL (1 << 4)
2338 # define MR1_BITS_5 (0 << 0)
2339 # define MR1_BITS_6 (1 << 0)
2340 # define MR1_BITS_7 (2 << 0)
2341 # define MR1_BITS_8 (3 << 0)
2342 # define MR1_PAR_EVN (0 << 2)
2343 # define MR1_PAR_ODD (1 << 2)
2344 # define MR1_PAR_NO (4 << 2)
2345 # define MR2_STOP1 (7 << 0)
2346 # define MR2_STOP2 (0xf << 0)
2347 #define SCCNXP_SR_REG (0x01)
2348 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2349 # define SR_RXRDY (1 << 0)
2350 # define SR_FULL (1 << 1)
2351 # define SR_TXRDY (1 << 2)
2352 # define SR_TXEMT (1 << 3)
2353 # define SR_OVR (1 << 4)
2354 # define SR_PE (1 << 5)
2355 # define SR_FE (1 << 6)
2356 # define SR_BRK (1 << 7)
2357 #define SCCNXP_CR_REG (0x02)
2358 # define CR_RX_ENABLE (1 << 0)
2359 # define CR_RX_DISABLE (1 << 1)
2360 # define CR_TX_ENABLE (1 << 2)
2361 # define CR_TX_DISABLE (1 << 3)
2362 # define CR_CMD_MRPTR1 (0x01 << 4)
2363 # define CR_CMD_RX_RESET (0x02 << 4)
2364 # define CR_CMD_TX_RESET (0x03 << 4)
2365 # define CR_CMD_STATUS_RESET (0x04 << 4)
2366 # define CR_CMD_BREAK_RESET (0x05 << 4)
2367 # define CR_CMD_START_BREAK (0x06 << 4)
2368 # define CR_CMD_STOP_BREAK (0x07 << 4)
2369 # define CR_CMD_MRPTR0 (0x0b << 4)
2370 #define SCCNXP_RHR_REG (0x03)
2371 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2372 #define SCCNXP_IPCR_REG (0x04)
2373 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2374 # define ACR_BAUD0 (0 << 7)
2375 # define ACR_BAUD1 (1 << 7)
2376 # define ACR_TIMER_MODE (6 << 4)
2377 #define SCCNXP_ISR_REG (0x05)
2378 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2379 # define IMR_TXRDY (1 << 0)
2380 # define IMR_RXRDY (1 << 1)
2381 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2382 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2383 #define SCCNXP_IPR_REG (0x0d)
2384 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2385 #define SCCNXP_SOP_REG (0x0e)
2386 #define SCCNXP_ROP_REG (0x0f)
2387 #define MCTRL_MASK(sig) (0xf << (sig))
2388 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2389 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2390 #define SCCNXP_HAVE_IO 0x00000001
2391 #define SCCNXP_HAVE_MR0 0x00000002
2392 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2393 #endif
2394 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2395 #endif
2396 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2397 #endif
2398 /* LDV_COMMENT_END_PREP */
2399
2400 /** CALLBACK SECTION request_irq **/
2401 /* content: static irqreturn_t sccnxp_ist(int irq, void *dev_id)*/
2402 /* LDV_COMMENT_BEGIN_PREP */
2403 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2404 #define SUPPORT_SYSRQ
2405 #endif
2406 #define SCCNXP_NAME "uart-sccnxp"
2407 #define SCCNXP_MAJOR 204
2408 #define SCCNXP_MINOR 205
2409 #define SCCNXP_MR_REG (0x00)
2410 # define MR0_BAUD_NORMAL (0 << 0)
2411 # define MR0_BAUD_EXT1 (1 << 0)
2412 # define MR0_BAUD_EXT2 (5 << 0)
2413 # define MR0_FIFO (1 << 3)
2414 # define MR0_TXLVL (1 << 4)
2415 # define MR1_BITS_5 (0 << 0)
2416 # define MR1_BITS_6 (1 << 0)
2417 # define MR1_BITS_7 (2 << 0)
2418 # define MR1_BITS_8 (3 << 0)
2419 # define MR1_PAR_EVN (0 << 2)
2420 # define MR1_PAR_ODD (1 << 2)
2421 # define MR1_PAR_NO (4 << 2)
2422 # define MR2_STOP1 (7 << 0)
2423 # define MR2_STOP2 (0xf << 0)
2424 #define SCCNXP_SR_REG (0x01)
2425 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2426 # define SR_RXRDY (1 << 0)
2427 # define SR_FULL (1 << 1)
2428 # define SR_TXRDY (1 << 2)
2429 # define SR_TXEMT (1 << 3)
2430 # define SR_OVR (1 << 4)
2431 # define SR_PE (1 << 5)
2432 # define SR_FE (1 << 6)
2433 # define SR_BRK (1 << 7)
2434 #define SCCNXP_CR_REG (0x02)
2435 # define CR_RX_ENABLE (1 << 0)
2436 # define CR_RX_DISABLE (1 << 1)
2437 # define CR_TX_ENABLE (1 << 2)
2438 # define CR_TX_DISABLE (1 << 3)
2439 # define CR_CMD_MRPTR1 (0x01 << 4)
2440 # define CR_CMD_RX_RESET (0x02 << 4)
2441 # define CR_CMD_TX_RESET (0x03 << 4)
2442 # define CR_CMD_STATUS_RESET (0x04 << 4)
2443 # define CR_CMD_BREAK_RESET (0x05 << 4)
2444 # define CR_CMD_START_BREAK (0x06 << 4)
2445 # define CR_CMD_STOP_BREAK (0x07 << 4)
2446 # define CR_CMD_MRPTR0 (0x0b << 4)
2447 #define SCCNXP_RHR_REG (0x03)
2448 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2449 #define SCCNXP_IPCR_REG (0x04)
2450 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2451 # define ACR_BAUD0 (0 << 7)
2452 # define ACR_BAUD1 (1 << 7)
2453 # define ACR_TIMER_MODE (6 << 4)
2454 #define SCCNXP_ISR_REG (0x05)
2455 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2456 # define IMR_TXRDY (1 << 0)
2457 # define IMR_RXRDY (1 << 1)
2458 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2459 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2460 #define SCCNXP_IPR_REG (0x0d)
2461 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2462 #define SCCNXP_SOP_REG (0x0e)
2463 #define SCCNXP_ROP_REG (0x0f)
2464 #define MCTRL_MASK(sig) (0xf << (sig))
2465 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2466 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2467 #define SCCNXP_HAVE_IO 0x00000001
2468 #define SCCNXP_HAVE_MR0 0x00000002
2469 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2470 #endif
2471 /* LDV_COMMENT_END_PREP */
2472 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_ist" */
2473 int var_sccnxp_ist_13_p0;
2474 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_ist" */
2475 void * var_sccnxp_ist_13_p1;
2476 /* LDV_COMMENT_BEGIN_PREP */
2477 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2478 #endif
2479 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2480 #endif
2481 /* LDV_COMMENT_END_PREP */
2482
2483
2484
2485
2486 /* LDV_COMMENT_END_VARIABLE_DECLARATION_PART */
2487 /* LDV_COMMENT_BEGIN_VARIABLE_INITIALIZING_PART */
2488 /*============================= VARIABLE INITIALIZING PART =============================*/
2489 LDV_IN_INTERRUPT=1;
2490
2491
2492
2493
2494 /* LDV_COMMENT_END_VARIABLE_INITIALIZING_PART */
2495 /* LDV_COMMENT_BEGIN_FUNCTION_CALL_SECTION */
2496 /*============================= FUNCTION CALL SECTION =============================*/
2497 /* LDV_COMMENT_FUNCTION_CALL Initialize LDV model. */
2498 ldv_initialize();
2499
2500
2501 int ldv_s_sccnxp_uart_driver_platform_driver = 0;
2502
2503
2504
2505
2506 while( nondet_int()
2507 || !(ldv_s_sccnxp_uart_driver_platform_driver == 0)
2508 ) {
2509
2510 switch(nondet_int()) {
2511
2512 case 0: {
2513
2514 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2515
2516
2517 /* content: static unsigned int sccnxp_tx_empty(struct uart_port *port)*/
2518 /* LDV_COMMENT_BEGIN_PREP */
2519 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2520 #define SUPPORT_SYSRQ
2521 #endif
2522 #define SCCNXP_NAME "uart-sccnxp"
2523 #define SCCNXP_MAJOR 204
2524 #define SCCNXP_MINOR 205
2525 #define SCCNXP_MR_REG (0x00)
2526 # define MR0_BAUD_NORMAL (0 << 0)
2527 # define MR0_BAUD_EXT1 (1 << 0)
2528 # define MR0_BAUD_EXT2 (5 << 0)
2529 # define MR0_FIFO (1 << 3)
2530 # define MR0_TXLVL (1 << 4)
2531 # define MR1_BITS_5 (0 << 0)
2532 # define MR1_BITS_6 (1 << 0)
2533 # define MR1_BITS_7 (2 << 0)
2534 # define MR1_BITS_8 (3 << 0)
2535 # define MR1_PAR_EVN (0 << 2)
2536 # define MR1_PAR_ODD (1 << 2)
2537 # define MR1_PAR_NO (4 << 2)
2538 # define MR2_STOP1 (7 << 0)
2539 # define MR2_STOP2 (0xf << 0)
2540 #define SCCNXP_SR_REG (0x01)
2541 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2542 # define SR_RXRDY (1 << 0)
2543 # define SR_FULL (1 << 1)
2544 # define SR_TXRDY (1 << 2)
2545 # define SR_TXEMT (1 << 3)
2546 # define SR_OVR (1 << 4)
2547 # define SR_PE (1 << 5)
2548 # define SR_FE (1 << 6)
2549 # define SR_BRK (1 << 7)
2550 #define SCCNXP_CR_REG (0x02)
2551 # define CR_RX_ENABLE (1 << 0)
2552 # define CR_RX_DISABLE (1 << 1)
2553 # define CR_TX_ENABLE (1 << 2)
2554 # define CR_TX_DISABLE (1 << 3)
2555 # define CR_CMD_MRPTR1 (0x01 << 4)
2556 # define CR_CMD_RX_RESET (0x02 << 4)
2557 # define CR_CMD_TX_RESET (0x03 << 4)
2558 # define CR_CMD_STATUS_RESET (0x04 << 4)
2559 # define CR_CMD_BREAK_RESET (0x05 << 4)
2560 # define CR_CMD_START_BREAK (0x06 << 4)
2561 # define CR_CMD_STOP_BREAK (0x07 << 4)
2562 # define CR_CMD_MRPTR0 (0x0b << 4)
2563 #define SCCNXP_RHR_REG (0x03)
2564 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2565 #define SCCNXP_IPCR_REG (0x04)
2566 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2567 # define ACR_BAUD0 (0 << 7)
2568 # define ACR_BAUD1 (1 << 7)
2569 # define ACR_TIMER_MODE (6 << 4)
2570 #define SCCNXP_ISR_REG (0x05)
2571 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2572 # define IMR_TXRDY (1 << 0)
2573 # define IMR_RXRDY (1 << 1)
2574 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2575 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2576 #define SCCNXP_IPR_REG (0x0d)
2577 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2578 #define SCCNXP_SOP_REG (0x0e)
2579 #define SCCNXP_ROP_REG (0x0f)
2580 #define MCTRL_MASK(sig) (0xf << (sig))
2581 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2582 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2583 #define SCCNXP_HAVE_IO 0x00000001
2584 #define SCCNXP_HAVE_MR0 0x00000002
2585 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2586 #endif
2587 /* LDV_COMMENT_END_PREP */
2588 /* LDV_COMMENT_FUNCTION_CALL Function from field "tx_empty" from driver structure with callbacks "sccnxp_ops" */
2589 ldv_handler_precall();
2590 sccnxp_tx_empty( var_group1);
2591 /* LDV_COMMENT_BEGIN_PREP */
2592 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2593 #endif
2594 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2595 #endif
2596 /* LDV_COMMENT_END_PREP */
2597
2598
2599
2600
2601 }
2602
2603 break;
2604 case 1: {
2605
2606 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2607
2608
2609 /* content: static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)*/
2610 /* LDV_COMMENT_BEGIN_PREP */
2611 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2612 #define SUPPORT_SYSRQ
2613 #endif
2614 #define SCCNXP_NAME "uart-sccnxp"
2615 #define SCCNXP_MAJOR 204
2616 #define SCCNXP_MINOR 205
2617 #define SCCNXP_MR_REG (0x00)
2618 # define MR0_BAUD_NORMAL (0 << 0)
2619 # define MR0_BAUD_EXT1 (1 << 0)
2620 # define MR0_BAUD_EXT2 (5 << 0)
2621 # define MR0_FIFO (1 << 3)
2622 # define MR0_TXLVL (1 << 4)
2623 # define MR1_BITS_5 (0 << 0)
2624 # define MR1_BITS_6 (1 << 0)
2625 # define MR1_BITS_7 (2 << 0)
2626 # define MR1_BITS_8 (3 << 0)
2627 # define MR1_PAR_EVN (0 << 2)
2628 # define MR1_PAR_ODD (1 << 2)
2629 # define MR1_PAR_NO (4 << 2)
2630 # define MR2_STOP1 (7 << 0)
2631 # define MR2_STOP2 (0xf << 0)
2632 #define SCCNXP_SR_REG (0x01)
2633 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2634 # define SR_RXRDY (1 << 0)
2635 # define SR_FULL (1 << 1)
2636 # define SR_TXRDY (1 << 2)
2637 # define SR_TXEMT (1 << 3)
2638 # define SR_OVR (1 << 4)
2639 # define SR_PE (1 << 5)
2640 # define SR_FE (1 << 6)
2641 # define SR_BRK (1 << 7)
2642 #define SCCNXP_CR_REG (0x02)
2643 # define CR_RX_ENABLE (1 << 0)
2644 # define CR_RX_DISABLE (1 << 1)
2645 # define CR_TX_ENABLE (1 << 2)
2646 # define CR_TX_DISABLE (1 << 3)
2647 # define CR_CMD_MRPTR1 (0x01 << 4)
2648 # define CR_CMD_RX_RESET (0x02 << 4)
2649 # define CR_CMD_TX_RESET (0x03 << 4)
2650 # define CR_CMD_STATUS_RESET (0x04 << 4)
2651 # define CR_CMD_BREAK_RESET (0x05 << 4)
2652 # define CR_CMD_START_BREAK (0x06 << 4)
2653 # define CR_CMD_STOP_BREAK (0x07 << 4)
2654 # define CR_CMD_MRPTR0 (0x0b << 4)
2655 #define SCCNXP_RHR_REG (0x03)
2656 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2657 #define SCCNXP_IPCR_REG (0x04)
2658 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2659 # define ACR_BAUD0 (0 << 7)
2660 # define ACR_BAUD1 (1 << 7)
2661 # define ACR_TIMER_MODE (6 << 4)
2662 #define SCCNXP_ISR_REG (0x05)
2663 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2664 # define IMR_TXRDY (1 << 0)
2665 # define IMR_RXRDY (1 << 1)
2666 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2667 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2668 #define SCCNXP_IPR_REG (0x0d)
2669 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2670 #define SCCNXP_SOP_REG (0x0e)
2671 #define SCCNXP_ROP_REG (0x0f)
2672 #define MCTRL_MASK(sig) (0xf << (sig))
2673 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2674 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2675 #define SCCNXP_HAVE_IO 0x00000001
2676 #define SCCNXP_HAVE_MR0 0x00000002
2677 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2678 #endif
2679 /* LDV_COMMENT_END_PREP */
2680 /* LDV_COMMENT_FUNCTION_CALL Function from field "set_mctrl" from driver structure with callbacks "sccnxp_ops" */
2681 ldv_handler_precall();
2682 sccnxp_set_mctrl( var_group1, var_sccnxp_set_mctrl_18_p1);
2683 /* LDV_COMMENT_BEGIN_PREP */
2684 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2685 #endif
2686 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2687 #endif
2688 /* LDV_COMMENT_END_PREP */
2689
2690
2691
2692
2693 }
2694
2695 break;
2696 case 2: {
2697
2698 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2699
2700
2701 /* content: static unsigned int sccnxp_get_mctrl(struct uart_port *port)*/
2702 /* LDV_COMMENT_BEGIN_PREP */
2703 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2704 #define SUPPORT_SYSRQ
2705 #endif
2706 #define SCCNXP_NAME "uart-sccnxp"
2707 #define SCCNXP_MAJOR 204
2708 #define SCCNXP_MINOR 205
2709 #define SCCNXP_MR_REG (0x00)
2710 # define MR0_BAUD_NORMAL (0 << 0)
2711 # define MR0_BAUD_EXT1 (1 << 0)
2712 # define MR0_BAUD_EXT2 (5 << 0)
2713 # define MR0_FIFO (1 << 3)
2714 # define MR0_TXLVL (1 << 4)
2715 # define MR1_BITS_5 (0 << 0)
2716 # define MR1_BITS_6 (1 << 0)
2717 # define MR1_BITS_7 (2 << 0)
2718 # define MR1_BITS_8 (3 << 0)
2719 # define MR1_PAR_EVN (0 << 2)
2720 # define MR1_PAR_ODD (1 << 2)
2721 # define MR1_PAR_NO (4 << 2)
2722 # define MR2_STOP1 (7 << 0)
2723 # define MR2_STOP2 (0xf << 0)
2724 #define SCCNXP_SR_REG (0x01)
2725 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2726 # define SR_RXRDY (1 << 0)
2727 # define SR_FULL (1 << 1)
2728 # define SR_TXRDY (1 << 2)
2729 # define SR_TXEMT (1 << 3)
2730 # define SR_OVR (1 << 4)
2731 # define SR_PE (1 << 5)
2732 # define SR_FE (1 << 6)
2733 # define SR_BRK (1 << 7)
2734 #define SCCNXP_CR_REG (0x02)
2735 # define CR_RX_ENABLE (1 << 0)
2736 # define CR_RX_DISABLE (1 << 1)
2737 # define CR_TX_ENABLE (1 << 2)
2738 # define CR_TX_DISABLE (1 << 3)
2739 # define CR_CMD_MRPTR1 (0x01 << 4)
2740 # define CR_CMD_RX_RESET (0x02 << 4)
2741 # define CR_CMD_TX_RESET (0x03 << 4)
2742 # define CR_CMD_STATUS_RESET (0x04 << 4)
2743 # define CR_CMD_BREAK_RESET (0x05 << 4)
2744 # define CR_CMD_START_BREAK (0x06 << 4)
2745 # define CR_CMD_STOP_BREAK (0x07 << 4)
2746 # define CR_CMD_MRPTR0 (0x0b << 4)
2747 #define SCCNXP_RHR_REG (0x03)
2748 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2749 #define SCCNXP_IPCR_REG (0x04)
2750 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2751 # define ACR_BAUD0 (0 << 7)
2752 # define ACR_BAUD1 (1 << 7)
2753 # define ACR_TIMER_MODE (6 << 4)
2754 #define SCCNXP_ISR_REG (0x05)
2755 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2756 # define IMR_TXRDY (1 << 0)
2757 # define IMR_RXRDY (1 << 1)
2758 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2759 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2760 #define SCCNXP_IPR_REG (0x0d)
2761 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2762 #define SCCNXP_SOP_REG (0x0e)
2763 #define SCCNXP_ROP_REG (0x0f)
2764 #define MCTRL_MASK(sig) (0xf << (sig))
2765 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2766 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2767 #define SCCNXP_HAVE_IO 0x00000001
2768 #define SCCNXP_HAVE_MR0 0x00000002
2769 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2770 #endif
2771 /* LDV_COMMENT_END_PREP */
2772 /* LDV_COMMENT_FUNCTION_CALL Function from field "get_mctrl" from driver structure with callbacks "sccnxp_ops" */
2773 ldv_handler_precall();
2774 sccnxp_get_mctrl( var_group1);
2775 /* LDV_COMMENT_BEGIN_PREP */
2776 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2777 #endif
2778 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2779 #endif
2780 /* LDV_COMMENT_END_PREP */
2781
2782
2783
2784
2785 }
2786
2787 break;
2788 case 3: {
2789
2790 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2791
2792
2793 /* content: static void sccnxp_stop_tx(struct uart_port *port)*/
2794 /* LDV_COMMENT_BEGIN_PREP */
2795 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2796 #define SUPPORT_SYSRQ
2797 #endif
2798 #define SCCNXP_NAME "uart-sccnxp"
2799 #define SCCNXP_MAJOR 204
2800 #define SCCNXP_MINOR 205
2801 #define SCCNXP_MR_REG (0x00)
2802 # define MR0_BAUD_NORMAL (0 << 0)
2803 # define MR0_BAUD_EXT1 (1 << 0)
2804 # define MR0_BAUD_EXT2 (5 << 0)
2805 # define MR0_FIFO (1 << 3)
2806 # define MR0_TXLVL (1 << 4)
2807 # define MR1_BITS_5 (0 << 0)
2808 # define MR1_BITS_6 (1 << 0)
2809 # define MR1_BITS_7 (2 << 0)
2810 # define MR1_BITS_8 (3 << 0)
2811 # define MR1_PAR_EVN (0 << 2)
2812 # define MR1_PAR_ODD (1 << 2)
2813 # define MR1_PAR_NO (4 << 2)
2814 # define MR2_STOP1 (7 << 0)
2815 # define MR2_STOP2 (0xf << 0)
2816 #define SCCNXP_SR_REG (0x01)
2817 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2818 # define SR_RXRDY (1 << 0)
2819 # define SR_FULL (1 << 1)
2820 # define SR_TXRDY (1 << 2)
2821 # define SR_TXEMT (1 << 3)
2822 # define SR_OVR (1 << 4)
2823 # define SR_PE (1 << 5)
2824 # define SR_FE (1 << 6)
2825 # define SR_BRK (1 << 7)
2826 #define SCCNXP_CR_REG (0x02)
2827 # define CR_RX_ENABLE (1 << 0)
2828 # define CR_RX_DISABLE (1 << 1)
2829 # define CR_TX_ENABLE (1 << 2)
2830 # define CR_TX_DISABLE (1 << 3)
2831 # define CR_CMD_MRPTR1 (0x01 << 4)
2832 # define CR_CMD_RX_RESET (0x02 << 4)
2833 # define CR_CMD_TX_RESET (0x03 << 4)
2834 # define CR_CMD_STATUS_RESET (0x04 << 4)
2835 # define CR_CMD_BREAK_RESET (0x05 << 4)
2836 # define CR_CMD_START_BREAK (0x06 << 4)
2837 # define CR_CMD_STOP_BREAK (0x07 << 4)
2838 # define CR_CMD_MRPTR0 (0x0b << 4)
2839 #define SCCNXP_RHR_REG (0x03)
2840 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2841 #define SCCNXP_IPCR_REG (0x04)
2842 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2843 # define ACR_BAUD0 (0 << 7)
2844 # define ACR_BAUD1 (1 << 7)
2845 # define ACR_TIMER_MODE (6 << 4)
2846 #define SCCNXP_ISR_REG (0x05)
2847 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2848 # define IMR_TXRDY (1 << 0)
2849 # define IMR_RXRDY (1 << 1)
2850 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2851 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2852 #define SCCNXP_IPR_REG (0x0d)
2853 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2854 #define SCCNXP_SOP_REG (0x0e)
2855 #define SCCNXP_ROP_REG (0x0f)
2856 #define MCTRL_MASK(sig) (0xf << (sig))
2857 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2858 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2859 #define SCCNXP_HAVE_IO 0x00000001
2860 #define SCCNXP_HAVE_MR0 0x00000002
2861 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2862 #endif
2863 /* LDV_COMMENT_END_PREP */
2864 /* LDV_COMMENT_FUNCTION_CALL Function from field "stop_tx" from driver structure with callbacks "sccnxp_ops" */
2865 ldv_handler_precall();
2866 sccnxp_stop_tx( var_group1);
2867 /* LDV_COMMENT_BEGIN_PREP */
2868 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2869 #endif
2870 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2871 #endif
2872 /* LDV_COMMENT_END_PREP */
2873
2874
2875
2876
2877 }
2878
2879 break;
2880 case 4: {
2881
2882 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2883
2884
2885 /* content: static void sccnxp_start_tx(struct uart_port *port)*/
2886 /* LDV_COMMENT_BEGIN_PREP */
2887 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2888 #define SUPPORT_SYSRQ
2889 #endif
2890 #define SCCNXP_NAME "uart-sccnxp"
2891 #define SCCNXP_MAJOR 204
2892 #define SCCNXP_MINOR 205
2893 #define SCCNXP_MR_REG (0x00)
2894 # define MR0_BAUD_NORMAL (0 << 0)
2895 # define MR0_BAUD_EXT1 (1 << 0)
2896 # define MR0_BAUD_EXT2 (5 << 0)
2897 # define MR0_FIFO (1 << 3)
2898 # define MR0_TXLVL (1 << 4)
2899 # define MR1_BITS_5 (0 << 0)
2900 # define MR1_BITS_6 (1 << 0)
2901 # define MR1_BITS_7 (2 << 0)
2902 # define MR1_BITS_8 (3 << 0)
2903 # define MR1_PAR_EVN (0 << 2)
2904 # define MR1_PAR_ODD (1 << 2)
2905 # define MR1_PAR_NO (4 << 2)
2906 # define MR2_STOP1 (7 << 0)
2907 # define MR2_STOP2 (0xf << 0)
2908 #define SCCNXP_SR_REG (0x01)
2909 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2910 # define SR_RXRDY (1 << 0)
2911 # define SR_FULL (1 << 1)
2912 # define SR_TXRDY (1 << 2)
2913 # define SR_TXEMT (1 << 3)
2914 # define SR_OVR (1 << 4)
2915 # define SR_PE (1 << 5)
2916 # define SR_FE (1 << 6)
2917 # define SR_BRK (1 << 7)
2918 #define SCCNXP_CR_REG (0x02)
2919 # define CR_RX_ENABLE (1 << 0)
2920 # define CR_RX_DISABLE (1 << 1)
2921 # define CR_TX_ENABLE (1 << 2)
2922 # define CR_TX_DISABLE (1 << 3)
2923 # define CR_CMD_MRPTR1 (0x01 << 4)
2924 # define CR_CMD_RX_RESET (0x02 << 4)
2925 # define CR_CMD_TX_RESET (0x03 << 4)
2926 # define CR_CMD_STATUS_RESET (0x04 << 4)
2927 # define CR_CMD_BREAK_RESET (0x05 << 4)
2928 # define CR_CMD_START_BREAK (0x06 << 4)
2929 # define CR_CMD_STOP_BREAK (0x07 << 4)
2930 # define CR_CMD_MRPTR0 (0x0b << 4)
2931 #define SCCNXP_RHR_REG (0x03)
2932 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2933 #define SCCNXP_IPCR_REG (0x04)
2934 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2935 # define ACR_BAUD0 (0 << 7)
2936 # define ACR_BAUD1 (1 << 7)
2937 # define ACR_TIMER_MODE (6 << 4)
2938 #define SCCNXP_ISR_REG (0x05)
2939 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2940 # define IMR_TXRDY (1 << 0)
2941 # define IMR_RXRDY (1 << 1)
2942 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2943 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2944 #define SCCNXP_IPR_REG (0x0d)
2945 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2946 #define SCCNXP_SOP_REG (0x0e)
2947 #define SCCNXP_ROP_REG (0x0f)
2948 #define MCTRL_MASK(sig) (0xf << (sig))
2949 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2950 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2951 #define SCCNXP_HAVE_IO 0x00000001
2952 #define SCCNXP_HAVE_MR0 0x00000002
2953 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2954 #endif
2955 /* LDV_COMMENT_END_PREP */
2956 /* LDV_COMMENT_FUNCTION_CALL Function from field "start_tx" from driver structure with callbacks "sccnxp_ops" */
2957 ldv_handler_precall();
2958 sccnxp_start_tx( var_group1);
2959 /* LDV_COMMENT_BEGIN_PREP */
2960 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2961 #endif
2962 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2963 #endif
2964 /* LDV_COMMENT_END_PREP */
2965
2966
2967
2968
2969 }
2970
2971 break;
2972 case 5: {
2973
2974 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2975
2976
2977 /* content: static void sccnxp_stop_rx(struct uart_port *port)*/
2978 /* LDV_COMMENT_BEGIN_PREP */
2979 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2980 #define SUPPORT_SYSRQ
2981 #endif
2982 #define SCCNXP_NAME "uart-sccnxp"
2983 #define SCCNXP_MAJOR 204
2984 #define SCCNXP_MINOR 205
2985 #define SCCNXP_MR_REG (0x00)
2986 # define MR0_BAUD_NORMAL (0 << 0)
2987 # define MR0_BAUD_EXT1 (1 << 0)
2988 # define MR0_BAUD_EXT2 (5 << 0)
2989 # define MR0_FIFO (1 << 3)
2990 # define MR0_TXLVL (1 << 4)
2991 # define MR1_BITS_5 (0 << 0)
2992 # define MR1_BITS_6 (1 << 0)
2993 # define MR1_BITS_7 (2 << 0)
2994 # define MR1_BITS_8 (3 << 0)
2995 # define MR1_PAR_EVN (0 << 2)
2996 # define MR1_PAR_ODD (1 << 2)
2997 # define MR1_PAR_NO (4 << 2)
2998 # define MR2_STOP1 (7 << 0)
2999 # define MR2_STOP2 (0xf << 0)
3000 #define SCCNXP_SR_REG (0x01)
3001 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3002 # define SR_RXRDY (1 << 0)
3003 # define SR_FULL (1 << 1)
3004 # define SR_TXRDY (1 << 2)
3005 # define SR_TXEMT (1 << 3)
3006 # define SR_OVR (1 << 4)
3007 # define SR_PE (1 << 5)
3008 # define SR_FE (1 << 6)
3009 # define SR_BRK (1 << 7)
3010 #define SCCNXP_CR_REG (0x02)
3011 # define CR_RX_ENABLE (1 << 0)
3012 # define CR_RX_DISABLE (1 << 1)
3013 # define CR_TX_ENABLE (1 << 2)
3014 # define CR_TX_DISABLE (1 << 3)
3015 # define CR_CMD_MRPTR1 (0x01 << 4)
3016 # define CR_CMD_RX_RESET (0x02 << 4)
3017 # define CR_CMD_TX_RESET (0x03 << 4)
3018 # define CR_CMD_STATUS_RESET (0x04 << 4)
3019 # define CR_CMD_BREAK_RESET (0x05 << 4)
3020 # define CR_CMD_START_BREAK (0x06 << 4)
3021 # define CR_CMD_STOP_BREAK (0x07 << 4)
3022 # define CR_CMD_MRPTR0 (0x0b << 4)
3023 #define SCCNXP_RHR_REG (0x03)
3024 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3025 #define SCCNXP_IPCR_REG (0x04)
3026 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3027 # define ACR_BAUD0 (0 << 7)
3028 # define ACR_BAUD1 (1 << 7)
3029 # define ACR_TIMER_MODE (6 << 4)
3030 #define SCCNXP_ISR_REG (0x05)
3031 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3032 # define IMR_TXRDY (1 << 0)
3033 # define IMR_RXRDY (1 << 1)
3034 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3035 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3036 #define SCCNXP_IPR_REG (0x0d)
3037 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3038 #define SCCNXP_SOP_REG (0x0e)
3039 #define SCCNXP_ROP_REG (0x0f)
3040 #define MCTRL_MASK(sig) (0xf << (sig))
3041 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3042 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3043 #define SCCNXP_HAVE_IO 0x00000001
3044 #define SCCNXP_HAVE_MR0 0x00000002
3045 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3046 #endif
3047 /* LDV_COMMENT_END_PREP */
3048 /* LDV_COMMENT_FUNCTION_CALL Function from field "stop_rx" from driver structure with callbacks "sccnxp_ops" */
3049 ldv_handler_precall();
3050 sccnxp_stop_rx( var_group1);
3051 /* LDV_COMMENT_BEGIN_PREP */
3052 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3053 #endif
3054 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3055 #endif
3056 /* LDV_COMMENT_END_PREP */
3057
3058
3059
3060
3061 }
3062
3063 break;
3064 case 6: {
3065
3066 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3067
3068
3069 /* content: static void sccnxp_break_ctl(struct uart_port *port, int break_state)*/
3070 /* LDV_COMMENT_BEGIN_PREP */
3071 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3072 #define SUPPORT_SYSRQ
3073 #endif
3074 #define SCCNXP_NAME "uart-sccnxp"
3075 #define SCCNXP_MAJOR 204
3076 #define SCCNXP_MINOR 205
3077 #define SCCNXP_MR_REG (0x00)
3078 # define MR0_BAUD_NORMAL (0 << 0)
3079 # define MR0_BAUD_EXT1 (1 << 0)
3080 # define MR0_BAUD_EXT2 (5 << 0)
3081 # define MR0_FIFO (1 << 3)
3082 # define MR0_TXLVL (1 << 4)
3083 # define MR1_BITS_5 (0 << 0)
3084 # define MR1_BITS_6 (1 << 0)
3085 # define MR1_BITS_7 (2 << 0)
3086 # define MR1_BITS_8 (3 << 0)
3087 # define MR1_PAR_EVN (0 << 2)
3088 # define MR1_PAR_ODD (1 << 2)
3089 # define MR1_PAR_NO (4 << 2)
3090 # define MR2_STOP1 (7 << 0)
3091 # define MR2_STOP2 (0xf << 0)
3092 #define SCCNXP_SR_REG (0x01)
3093 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3094 # define SR_RXRDY (1 << 0)
3095 # define SR_FULL (1 << 1)
3096 # define SR_TXRDY (1 << 2)
3097 # define SR_TXEMT (1 << 3)
3098 # define SR_OVR (1 << 4)
3099 # define SR_PE (1 << 5)
3100 # define SR_FE (1 << 6)
3101 # define SR_BRK (1 << 7)
3102 #define SCCNXP_CR_REG (0x02)
3103 # define CR_RX_ENABLE (1 << 0)
3104 # define CR_RX_DISABLE (1 << 1)
3105 # define CR_TX_ENABLE (1 << 2)
3106 # define CR_TX_DISABLE (1 << 3)
3107 # define CR_CMD_MRPTR1 (0x01 << 4)
3108 # define CR_CMD_RX_RESET (0x02 << 4)
3109 # define CR_CMD_TX_RESET (0x03 << 4)
3110 # define CR_CMD_STATUS_RESET (0x04 << 4)
3111 # define CR_CMD_BREAK_RESET (0x05 << 4)
3112 # define CR_CMD_START_BREAK (0x06 << 4)
3113 # define CR_CMD_STOP_BREAK (0x07 << 4)
3114 # define CR_CMD_MRPTR0 (0x0b << 4)
3115 #define SCCNXP_RHR_REG (0x03)
3116 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3117 #define SCCNXP_IPCR_REG (0x04)
3118 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3119 # define ACR_BAUD0 (0 << 7)
3120 # define ACR_BAUD1 (1 << 7)
3121 # define ACR_TIMER_MODE (6 << 4)
3122 #define SCCNXP_ISR_REG (0x05)
3123 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3124 # define IMR_TXRDY (1 << 0)
3125 # define IMR_RXRDY (1 << 1)
3126 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3127 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3128 #define SCCNXP_IPR_REG (0x0d)
3129 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3130 #define SCCNXP_SOP_REG (0x0e)
3131 #define SCCNXP_ROP_REG (0x0f)
3132 #define MCTRL_MASK(sig) (0xf << (sig))
3133 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3134 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3135 #define SCCNXP_HAVE_IO 0x00000001
3136 #define SCCNXP_HAVE_MR0 0x00000002
3137 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3138 #endif
3139 /* LDV_COMMENT_END_PREP */
3140 /* LDV_COMMENT_FUNCTION_CALL Function from field "break_ctl" from driver structure with callbacks "sccnxp_ops" */
3141 ldv_handler_precall();
3142 sccnxp_break_ctl( var_group1, var_sccnxp_break_ctl_20_p1);
3143 /* LDV_COMMENT_BEGIN_PREP */
3144 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3145 #endif
3146 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3147 #endif
3148 /* LDV_COMMENT_END_PREP */
3149
3150
3151
3152
3153 }
3154
3155 break;
3156 case 7: {
3157
3158 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3159
3160
3161 /* content: static int sccnxp_startup(struct uart_port *port)*/
3162 /* LDV_COMMENT_BEGIN_PREP */
3163 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3164 #define SUPPORT_SYSRQ
3165 #endif
3166 #define SCCNXP_NAME "uart-sccnxp"
3167 #define SCCNXP_MAJOR 204
3168 #define SCCNXP_MINOR 205
3169 #define SCCNXP_MR_REG (0x00)
3170 # define MR0_BAUD_NORMAL (0 << 0)
3171 # define MR0_BAUD_EXT1 (1 << 0)
3172 # define MR0_BAUD_EXT2 (5 << 0)
3173 # define MR0_FIFO (1 << 3)
3174 # define MR0_TXLVL (1 << 4)
3175 # define MR1_BITS_5 (0 << 0)
3176 # define MR1_BITS_6 (1 << 0)
3177 # define MR1_BITS_7 (2 << 0)
3178 # define MR1_BITS_8 (3 << 0)
3179 # define MR1_PAR_EVN (0 << 2)
3180 # define MR1_PAR_ODD (1 << 2)
3181 # define MR1_PAR_NO (4 << 2)
3182 # define MR2_STOP1 (7 << 0)
3183 # define MR2_STOP2 (0xf << 0)
3184 #define SCCNXP_SR_REG (0x01)
3185 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3186 # define SR_RXRDY (1 << 0)
3187 # define SR_FULL (1 << 1)
3188 # define SR_TXRDY (1 << 2)
3189 # define SR_TXEMT (1 << 3)
3190 # define SR_OVR (1 << 4)
3191 # define SR_PE (1 << 5)
3192 # define SR_FE (1 << 6)
3193 # define SR_BRK (1 << 7)
3194 #define SCCNXP_CR_REG (0x02)
3195 # define CR_RX_ENABLE (1 << 0)
3196 # define CR_RX_DISABLE (1 << 1)
3197 # define CR_TX_ENABLE (1 << 2)
3198 # define CR_TX_DISABLE (1 << 3)
3199 # define CR_CMD_MRPTR1 (0x01 << 4)
3200 # define CR_CMD_RX_RESET (0x02 << 4)
3201 # define CR_CMD_TX_RESET (0x03 << 4)
3202 # define CR_CMD_STATUS_RESET (0x04 << 4)
3203 # define CR_CMD_BREAK_RESET (0x05 << 4)
3204 # define CR_CMD_START_BREAK (0x06 << 4)
3205 # define CR_CMD_STOP_BREAK (0x07 << 4)
3206 # define CR_CMD_MRPTR0 (0x0b << 4)
3207 #define SCCNXP_RHR_REG (0x03)
3208 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3209 #define SCCNXP_IPCR_REG (0x04)
3210 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3211 # define ACR_BAUD0 (0 << 7)
3212 # define ACR_BAUD1 (1 << 7)
3213 # define ACR_TIMER_MODE (6 << 4)
3214 #define SCCNXP_ISR_REG (0x05)
3215 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3216 # define IMR_TXRDY (1 << 0)
3217 # define IMR_RXRDY (1 << 1)
3218 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3219 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3220 #define SCCNXP_IPR_REG (0x0d)
3221 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3222 #define SCCNXP_SOP_REG (0x0e)
3223 #define SCCNXP_ROP_REG (0x0f)
3224 #define MCTRL_MASK(sig) (0xf << (sig))
3225 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3226 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3227 #define SCCNXP_HAVE_IO 0x00000001
3228 #define SCCNXP_HAVE_MR0 0x00000002
3229 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3230 #endif
3231 /* LDV_COMMENT_END_PREP */
3232 /* LDV_COMMENT_FUNCTION_CALL Function from field "startup" from driver structure with callbacks "sccnxp_ops" */
3233 ldv_handler_precall();
3234 sccnxp_startup( var_group1);
3235 /* LDV_COMMENT_BEGIN_PREP */
3236 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3237 #endif
3238 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3239 #endif
3240 /* LDV_COMMENT_END_PREP */
3241
3242
3243
3244
3245 }
3246
3247 break;
3248 case 8: {
3249
3250 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3251
3252
3253 /* content: static void sccnxp_shutdown(struct uart_port *port)*/
3254 /* LDV_COMMENT_BEGIN_PREP */
3255 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3256 #define SUPPORT_SYSRQ
3257 #endif
3258 #define SCCNXP_NAME "uart-sccnxp"
3259 #define SCCNXP_MAJOR 204
3260 #define SCCNXP_MINOR 205
3261 #define SCCNXP_MR_REG (0x00)
3262 # define MR0_BAUD_NORMAL (0 << 0)
3263 # define MR0_BAUD_EXT1 (1 << 0)
3264 # define MR0_BAUD_EXT2 (5 << 0)
3265 # define MR0_FIFO (1 << 3)
3266 # define MR0_TXLVL (1 << 4)
3267 # define MR1_BITS_5 (0 << 0)
3268 # define MR1_BITS_6 (1 << 0)
3269 # define MR1_BITS_7 (2 << 0)
3270 # define MR1_BITS_8 (3 << 0)
3271 # define MR1_PAR_EVN (0 << 2)
3272 # define MR1_PAR_ODD (1 << 2)
3273 # define MR1_PAR_NO (4 << 2)
3274 # define MR2_STOP1 (7 << 0)
3275 # define MR2_STOP2 (0xf << 0)
3276 #define SCCNXP_SR_REG (0x01)
3277 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3278 # define SR_RXRDY (1 << 0)
3279 # define SR_FULL (1 << 1)
3280 # define SR_TXRDY (1 << 2)
3281 # define SR_TXEMT (1 << 3)
3282 # define SR_OVR (1 << 4)
3283 # define SR_PE (1 << 5)
3284 # define SR_FE (1 << 6)
3285 # define SR_BRK (1 << 7)
3286 #define SCCNXP_CR_REG (0x02)
3287 # define CR_RX_ENABLE (1 << 0)
3288 # define CR_RX_DISABLE (1 << 1)
3289 # define CR_TX_ENABLE (1 << 2)
3290 # define CR_TX_DISABLE (1 << 3)
3291 # define CR_CMD_MRPTR1 (0x01 << 4)
3292 # define CR_CMD_RX_RESET (0x02 << 4)
3293 # define CR_CMD_TX_RESET (0x03 << 4)
3294 # define CR_CMD_STATUS_RESET (0x04 << 4)
3295 # define CR_CMD_BREAK_RESET (0x05 << 4)
3296 # define CR_CMD_START_BREAK (0x06 << 4)
3297 # define CR_CMD_STOP_BREAK (0x07 << 4)
3298 # define CR_CMD_MRPTR0 (0x0b << 4)
3299 #define SCCNXP_RHR_REG (0x03)
3300 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3301 #define SCCNXP_IPCR_REG (0x04)
3302 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3303 # define ACR_BAUD0 (0 << 7)
3304 # define ACR_BAUD1 (1 << 7)
3305 # define ACR_TIMER_MODE (6 << 4)
3306 #define SCCNXP_ISR_REG (0x05)
3307 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3308 # define IMR_TXRDY (1 << 0)
3309 # define IMR_RXRDY (1 << 1)
3310 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3311 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3312 #define SCCNXP_IPR_REG (0x0d)
3313 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3314 #define SCCNXP_SOP_REG (0x0e)
3315 #define SCCNXP_ROP_REG (0x0f)
3316 #define MCTRL_MASK(sig) (0xf << (sig))
3317 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3318 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3319 #define SCCNXP_HAVE_IO 0x00000001
3320 #define SCCNXP_HAVE_MR0 0x00000002
3321 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3322 #endif
3323 /* LDV_COMMENT_END_PREP */
3324 /* LDV_COMMENT_FUNCTION_CALL Function from field "shutdown" from driver structure with callbacks "sccnxp_ops" */
3325 ldv_handler_precall();
3326 sccnxp_shutdown( var_group1);
3327 /* LDV_COMMENT_BEGIN_PREP */
3328 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3329 #endif
3330 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3331 #endif
3332 /* LDV_COMMENT_END_PREP */
3333
3334
3335
3336
3337 }
3338
3339 break;
3340 case 9: {
3341
3342 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3343
3344
3345 /* content: static void sccnxp_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)*/
3346 /* LDV_COMMENT_BEGIN_PREP */
3347 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3348 #define SUPPORT_SYSRQ
3349 #endif
3350 #define SCCNXP_NAME "uart-sccnxp"
3351 #define SCCNXP_MAJOR 204
3352 #define SCCNXP_MINOR 205
3353 #define SCCNXP_MR_REG (0x00)
3354 # define MR0_BAUD_NORMAL (0 << 0)
3355 # define MR0_BAUD_EXT1 (1 << 0)
3356 # define MR0_BAUD_EXT2 (5 << 0)
3357 # define MR0_FIFO (1 << 3)
3358 # define MR0_TXLVL (1 << 4)
3359 # define MR1_BITS_5 (0 << 0)
3360 # define MR1_BITS_6 (1 << 0)
3361 # define MR1_BITS_7 (2 << 0)
3362 # define MR1_BITS_8 (3 << 0)
3363 # define MR1_PAR_EVN (0 << 2)
3364 # define MR1_PAR_ODD (1 << 2)
3365 # define MR1_PAR_NO (4 << 2)
3366 # define MR2_STOP1 (7 << 0)
3367 # define MR2_STOP2 (0xf << 0)
3368 #define SCCNXP_SR_REG (0x01)
3369 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3370 # define SR_RXRDY (1 << 0)
3371 # define SR_FULL (1 << 1)
3372 # define SR_TXRDY (1 << 2)
3373 # define SR_TXEMT (1 << 3)
3374 # define SR_OVR (1 << 4)
3375 # define SR_PE (1 << 5)
3376 # define SR_FE (1 << 6)
3377 # define SR_BRK (1 << 7)
3378 #define SCCNXP_CR_REG (0x02)
3379 # define CR_RX_ENABLE (1 << 0)
3380 # define CR_RX_DISABLE (1 << 1)
3381 # define CR_TX_ENABLE (1 << 2)
3382 # define CR_TX_DISABLE (1 << 3)
3383 # define CR_CMD_MRPTR1 (0x01 << 4)
3384 # define CR_CMD_RX_RESET (0x02 << 4)
3385 # define CR_CMD_TX_RESET (0x03 << 4)
3386 # define CR_CMD_STATUS_RESET (0x04 << 4)
3387 # define CR_CMD_BREAK_RESET (0x05 << 4)
3388 # define CR_CMD_START_BREAK (0x06 << 4)
3389 # define CR_CMD_STOP_BREAK (0x07 << 4)
3390 # define CR_CMD_MRPTR0 (0x0b << 4)
3391 #define SCCNXP_RHR_REG (0x03)
3392 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3393 #define SCCNXP_IPCR_REG (0x04)
3394 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3395 # define ACR_BAUD0 (0 << 7)
3396 # define ACR_BAUD1 (1 << 7)
3397 # define ACR_TIMER_MODE (6 << 4)
3398 #define SCCNXP_ISR_REG (0x05)
3399 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3400 # define IMR_TXRDY (1 << 0)
3401 # define IMR_RXRDY (1 << 1)
3402 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3403 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3404 #define SCCNXP_IPR_REG (0x0d)
3405 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3406 #define SCCNXP_SOP_REG (0x0e)
3407 #define SCCNXP_ROP_REG (0x0f)
3408 #define MCTRL_MASK(sig) (0xf << (sig))
3409 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3410 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3411 #define SCCNXP_HAVE_IO 0x00000001
3412 #define SCCNXP_HAVE_MR0 0x00000002
3413 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3414 #endif
3415 /* LDV_COMMENT_END_PREP */
3416 /* LDV_COMMENT_FUNCTION_CALL Function from field "set_termios" from driver structure with callbacks "sccnxp_ops" */
3417 ldv_handler_precall();
3418 sccnxp_set_termios( var_group1, var_group2, var_sccnxp_set_termios_21_p2);
3419 /* LDV_COMMENT_BEGIN_PREP */
3420 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3421 #endif
3422 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3423 #endif
3424 /* LDV_COMMENT_END_PREP */
3425
3426
3427
3428
3429 }
3430
3431 break;
3432 case 10: {
3433
3434 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3435
3436
3437 /* content: static const char *sccnxp_type(struct uart_port *port)*/
3438 /* LDV_COMMENT_BEGIN_PREP */
3439 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3440 #define SUPPORT_SYSRQ
3441 #endif
3442 #define SCCNXP_NAME "uart-sccnxp"
3443 #define SCCNXP_MAJOR 204
3444 #define SCCNXP_MINOR 205
3445 #define SCCNXP_MR_REG (0x00)
3446 # define MR0_BAUD_NORMAL (0 << 0)
3447 # define MR0_BAUD_EXT1 (1 << 0)
3448 # define MR0_BAUD_EXT2 (5 << 0)
3449 # define MR0_FIFO (1 << 3)
3450 # define MR0_TXLVL (1 << 4)
3451 # define MR1_BITS_5 (0 << 0)
3452 # define MR1_BITS_6 (1 << 0)
3453 # define MR1_BITS_7 (2 << 0)
3454 # define MR1_BITS_8 (3 << 0)
3455 # define MR1_PAR_EVN (0 << 2)
3456 # define MR1_PAR_ODD (1 << 2)
3457 # define MR1_PAR_NO (4 << 2)
3458 # define MR2_STOP1 (7 << 0)
3459 # define MR2_STOP2 (0xf << 0)
3460 #define SCCNXP_SR_REG (0x01)
3461 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3462 # define SR_RXRDY (1 << 0)
3463 # define SR_FULL (1 << 1)
3464 # define SR_TXRDY (1 << 2)
3465 # define SR_TXEMT (1 << 3)
3466 # define SR_OVR (1 << 4)
3467 # define SR_PE (1 << 5)
3468 # define SR_FE (1 << 6)
3469 # define SR_BRK (1 << 7)
3470 #define SCCNXP_CR_REG (0x02)
3471 # define CR_RX_ENABLE (1 << 0)
3472 # define CR_RX_DISABLE (1 << 1)
3473 # define CR_TX_ENABLE (1 << 2)
3474 # define CR_TX_DISABLE (1 << 3)
3475 # define CR_CMD_MRPTR1 (0x01 << 4)
3476 # define CR_CMD_RX_RESET (0x02 << 4)
3477 # define CR_CMD_TX_RESET (0x03 << 4)
3478 # define CR_CMD_STATUS_RESET (0x04 << 4)
3479 # define CR_CMD_BREAK_RESET (0x05 << 4)
3480 # define CR_CMD_START_BREAK (0x06 << 4)
3481 # define CR_CMD_STOP_BREAK (0x07 << 4)
3482 # define CR_CMD_MRPTR0 (0x0b << 4)
3483 #define SCCNXP_RHR_REG (0x03)
3484 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3485 #define SCCNXP_IPCR_REG (0x04)
3486 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3487 # define ACR_BAUD0 (0 << 7)
3488 # define ACR_BAUD1 (1 << 7)
3489 # define ACR_TIMER_MODE (6 << 4)
3490 #define SCCNXP_ISR_REG (0x05)
3491 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3492 # define IMR_TXRDY (1 << 0)
3493 # define IMR_RXRDY (1 << 1)
3494 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3495 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3496 #define SCCNXP_IPR_REG (0x0d)
3497 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3498 #define SCCNXP_SOP_REG (0x0e)
3499 #define SCCNXP_ROP_REG (0x0f)
3500 #define MCTRL_MASK(sig) (0xf << (sig))
3501 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3502 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3503 #define SCCNXP_HAVE_IO 0x00000001
3504 #define SCCNXP_HAVE_MR0 0x00000002
3505 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3506 #endif
3507 /* LDV_COMMENT_END_PREP */
3508 /* LDV_COMMENT_FUNCTION_CALL Function from field "type" from driver structure with callbacks "sccnxp_ops" */
3509 ldv_handler_precall();
3510 sccnxp_type( var_group1);
3511 /* LDV_COMMENT_BEGIN_PREP */
3512 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3513 #endif
3514 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3515 #endif
3516 /* LDV_COMMENT_END_PREP */
3517
3518
3519
3520
3521 }
3522
3523 break;
3524 case 11: {
3525
3526 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3527
3528
3529 /* content: static void sccnxp_release_port(struct uart_port *port)*/
3530 /* LDV_COMMENT_BEGIN_PREP */
3531 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3532 #define SUPPORT_SYSRQ
3533 #endif
3534 #define SCCNXP_NAME "uart-sccnxp"
3535 #define SCCNXP_MAJOR 204
3536 #define SCCNXP_MINOR 205
3537 #define SCCNXP_MR_REG (0x00)
3538 # define MR0_BAUD_NORMAL (0 << 0)
3539 # define MR0_BAUD_EXT1 (1 << 0)
3540 # define MR0_BAUD_EXT2 (5 << 0)
3541 # define MR0_FIFO (1 << 3)
3542 # define MR0_TXLVL (1 << 4)
3543 # define MR1_BITS_5 (0 << 0)
3544 # define MR1_BITS_6 (1 << 0)
3545 # define MR1_BITS_7 (2 << 0)
3546 # define MR1_BITS_8 (3 << 0)
3547 # define MR1_PAR_EVN (0 << 2)
3548 # define MR1_PAR_ODD (1 << 2)
3549 # define MR1_PAR_NO (4 << 2)
3550 # define MR2_STOP1 (7 << 0)
3551 # define MR2_STOP2 (0xf << 0)
3552 #define SCCNXP_SR_REG (0x01)
3553 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3554 # define SR_RXRDY (1 << 0)
3555 # define SR_FULL (1 << 1)
3556 # define SR_TXRDY (1 << 2)
3557 # define SR_TXEMT (1 << 3)
3558 # define SR_OVR (1 << 4)
3559 # define SR_PE (1 << 5)
3560 # define SR_FE (1 << 6)
3561 # define SR_BRK (1 << 7)
3562 #define SCCNXP_CR_REG (0x02)
3563 # define CR_RX_ENABLE (1 << 0)
3564 # define CR_RX_DISABLE (1 << 1)
3565 # define CR_TX_ENABLE (1 << 2)
3566 # define CR_TX_DISABLE (1 << 3)
3567 # define CR_CMD_MRPTR1 (0x01 << 4)
3568 # define CR_CMD_RX_RESET (0x02 << 4)
3569 # define CR_CMD_TX_RESET (0x03 << 4)
3570 # define CR_CMD_STATUS_RESET (0x04 << 4)
3571 # define CR_CMD_BREAK_RESET (0x05 << 4)
3572 # define CR_CMD_START_BREAK (0x06 << 4)
3573 # define CR_CMD_STOP_BREAK (0x07 << 4)
3574 # define CR_CMD_MRPTR0 (0x0b << 4)
3575 #define SCCNXP_RHR_REG (0x03)
3576 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3577 #define SCCNXP_IPCR_REG (0x04)
3578 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3579 # define ACR_BAUD0 (0 << 7)
3580 # define ACR_BAUD1 (1 << 7)
3581 # define ACR_TIMER_MODE (6 << 4)
3582 #define SCCNXP_ISR_REG (0x05)
3583 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3584 # define IMR_TXRDY (1 << 0)
3585 # define IMR_RXRDY (1 << 1)
3586 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3587 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3588 #define SCCNXP_IPR_REG (0x0d)
3589 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3590 #define SCCNXP_SOP_REG (0x0e)
3591 #define SCCNXP_ROP_REG (0x0f)
3592 #define MCTRL_MASK(sig) (0xf << (sig))
3593 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3594 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3595 #define SCCNXP_HAVE_IO 0x00000001
3596 #define SCCNXP_HAVE_MR0 0x00000002
3597 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3598 #endif
3599 /* LDV_COMMENT_END_PREP */
3600 /* LDV_COMMENT_FUNCTION_CALL Function from field "release_port" from driver structure with callbacks "sccnxp_ops" */
3601 ldv_handler_precall();
3602 sccnxp_release_port( var_group1);
3603 /* LDV_COMMENT_BEGIN_PREP */
3604 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3605 #endif
3606 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3607 #endif
3608 /* LDV_COMMENT_END_PREP */
3609
3610
3611
3612
3613 }
3614
3615 break;
3616 case 12: {
3617
3618 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3619
3620
3621 /* content: static int sccnxp_request_port(struct uart_port *port)*/
3622 /* LDV_COMMENT_BEGIN_PREP */
3623 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3624 #define SUPPORT_SYSRQ
3625 #endif
3626 #define SCCNXP_NAME "uart-sccnxp"
3627 #define SCCNXP_MAJOR 204
3628 #define SCCNXP_MINOR 205
3629 #define SCCNXP_MR_REG (0x00)
3630 # define MR0_BAUD_NORMAL (0 << 0)
3631 # define MR0_BAUD_EXT1 (1 << 0)
3632 # define MR0_BAUD_EXT2 (5 << 0)
3633 # define MR0_FIFO (1 << 3)
3634 # define MR0_TXLVL (1 << 4)
3635 # define MR1_BITS_5 (0 << 0)
3636 # define MR1_BITS_6 (1 << 0)
3637 # define MR1_BITS_7 (2 << 0)
3638 # define MR1_BITS_8 (3 << 0)
3639 # define MR1_PAR_EVN (0 << 2)
3640 # define MR1_PAR_ODD (1 << 2)
3641 # define MR1_PAR_NO (4 << 2)
3642 # define MR2_STOP1 (7 << 0)
3643 # define MR2_STOP2 (0xf << 0)
3644 #define SCCNXP_SR_REG (0x01)
3645 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3646 # define SR_RXRDY (1 << 0)
3647 # define SR_FULL (1 << 1)
3648 # define SR_TXRDY (1 << 2)
3649 # define SR_TXEMT (1 << 3)
3650 # define SR_OVR (1 << 4)
3651 # define SR_PE (1 << 5)
3652 # define SR_FE (1 << 6)
3653 # define SR_BRK (1 << 7)
3654 #define SCCNXP_CR_REG (0x02)
3655 # define CR_RX_ENABLE (1 << 0)
3656 # define CR_RX_DISABLE (1 << 1)
3657 # define CR_TX_ENABLE (1 << 2)
3658 # define CR_TX_DISABLE (1 << 3)
3659 # define CR_CMD_MRPTR1 (0x01 << 4)
3660 # define CR_CMD_RX_RESET (0x02 << 4)
3661 # define CR_CMD_TX_RESET (0x03 << 4)
3662 # define CR_CMD_STATUS_RESET (0x04 << 4)
3663 # define CR_CMD_BREAK_RESET (0x05 << 4)
3664 # define CR_CMD_START_BREAK (0x06 << 4)
3665 # define CR_CMD_STOP_BREAK (0x07 << 4)
3666 # define CR_CMD_MRPTR0 (0x0b << 4)
3667 #define SCCNXP_RHR_REG (0x03)
3668 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3669 #define SCCNXP_IPCR_REG (0x04)
3670 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3671 # define ACR_BAUD0 (0 << 7)
3672 # define ACR_BAUD1 (1 << 7)
3673 # define ACR_TIMER_MODE (6 << 4)
3674 #define SCCNXP_ISR_REG (0x05)
3675 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3676 # define IMR_TXRDY (1 << 0)
3677 # define IMR_RXRDY (1 << 1)
3678 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3679 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3680 #define SCCNXP_IPR_REG (0x0d)
3681 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3682 #define SCCNXP_SOP_REG (0x0e)
3683 #define SCCNXP_ROP_REG (0x0f)
3684 #define MCTRL_MASK(sig) (0xf << (sig))
3685 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3686 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3687 #define SCCNXP_HAVE_IO 0x00000001
3688 #define SCCNXP_HAVE_MR0 0x00000002
3689 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3690 #endif
3691 /* LDV_COMMENT_END_PREP */
3692 /* LDV_COMMENT_FUNCTION_CALL Function from field "request_port" from driver structure with callbacks "sccnxp_ops" */
3693 ldv_handler_precall();
3694 sccnxp_request_port( var_group1);
3695 /* LDV_COMMENT_BEGIN_PREP */
3696 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3697 #endif
3698 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3699 #endif
3700 /* LDV_COMMENT_END_PREP */
3701
3702
3703
3704
3705 }
3706
3707 break;
3708 case 13: {
3709
3710 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3711
3712
3713 /* content: static void sccnxp_config_port(struct uart_port *port, int flags)*/
3714 /* LDV_COMMENT_BEGIN_PREP */
3715 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3716 #define SUPPORT_SYSRQ
3717 #endif
3718 #define SCCNXP_NAME "uart-sccnxp"
3719 #define SCCNXP_MAJOR 204
3720 #define SCCNXP_MINOR 205
3721 #define SCCNXP_MR_REG (0x00)
3722 # define MR0_BAUD_NORMAL (0 << 0)
3723 # define MR0_BAUD_EXT1 (1 << 0)
3724 # define MR0_BAUD_EXT2 (5 << 0)
3725 # define MR0_FIFO (1 << 3)
3726 # define MR0_TXLVL (1 << 4)
3727 # define MR1_BITS_5 (0 << 0)
3728 # define MR1_BITS_6 (1 << 0)
3729 # define MR1_BITS_7 (2 << 0)
3730 # define MR1_BITS_8 (3 << 0)
3731 # define MR1_PAR_EVN (0 << 2)
3732 # define MR1_PAR_ODD (1 << 2)
3733 # define MR1_PAR_NO (4 << 2)
3734 # define MR2_STOP1 (7 << 0)
3735 # define MR2_STOP2 (0xf << 0)
3736 #define SCCNXP_SR_REG (0x01)
3737 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3738 # define SR_RXRDY (1 << 0)
3739 # define SR_FULL (1 << 1)
3740 # define SR_TXRDY (1 << 2)
3741 # define SR_TXEMT (1 << 3)
3742 # define SR_OVR (1 << 4)
3743 # define SR_PE (1 << 5)
3744 # define SR_FE (1 << 6)
3745 # define SR_BRK (1 << 7)
3746 #define SCCNXP_CR_REG (0x02)
3747 # define CR_RX_ENABLE (1 << 0)
3748 # define CR_RX_DISABLE (1 << 1)
3749 # define CR_TX_ENABLE (1 << 2)
3750 # define CR_TX_DISABLE (1 << 3)
3751 # define CR_CMD_MRPTR1 (0x01 << 4)
3752 # define CR_CMD_RX_RESET (0x02 << 4)
3753 # define CR_CMD_TX_RESET (0x03 << 4)
3754 # define CR_CMD_STATUS_RESET (0x04 << 4)
3755 # define CR_CMD_BREAK_RESET (0x05 << 4)
3756 # define CR_CMD_START_BREAK (0x06 << 4)
3757 # define CR_CMD_STOP_BREAK (0x07 << 4)
3758 # define CR_CMD_MRPTR0 (0x0b << 4)
3759 #define SCCNXP_RHR_REG (0x03)
3760 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3761 #define SCCNXP_IPCR_REG (0x04)
3762 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3763 # define ACR_BAUD0 (0 << 7)
3764 # define ACR_BAUD1 (1 << 7)
3765 # define ACR_TIMER_MODE (6 << 4)
3766 #define SCCNXP_ISR_REG (0x05)
3767 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3768 # define IMR_TXRDY (1 << 0)
3769 # define IMR_RXRDY (1 << 1)
3770 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3771 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3772 #define SCCNXP_IPR_REG (0x0d)
3773 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3774 #define SCCNXP_SOP_REG (0x0e)
3775 #define SCCNXP_ROP_REG (0x0f)
3776 #define MCTRL_MASK(sig) (0xf << (sig))
3777 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3778 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3779 #define SCCNXP_HAVE_IO 0x00000001
3780 #define SCCNXP_HAVE_MR0 0x00000002
3781 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3782 #endif
3783 /* LDV_COMMENT_END_PREP */
3784 /* LDV_COMMENT_FUNCTION_CALL Function from field "config_port" from driver structure with callbacks "sccnxp_ops" */
3785 ldv_handler_precall();
3786 sccnxp_config_port( var_group1, var_sccnxp_config_port_27_p1);
3787 /* LDV_COMMENT_BEGIN_PREP */
3788 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3789 #endif
3790 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3791 #endif
3792 /* LDV_COMMENT_END_PREP */
3793
3794
3795
3796
3797 }
3798
3799 break;
3800 case 14: {
3801
3802 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3803
3804
3805 /* content: static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)*/
3806 /* LDV_COMMENT_BEGIN_PREP */
3807 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3808 #define SUPPORT_SYSRQ
3809 #endif
3810 #define SCCNXP_NAME "uart-sccnxp"
3811 #define SCCNXP_MAJOR 204
3812 #define SCCNXP_MINOR 205
3813 #define SCCNXP_MR_REG (0x00)
3814 # define MR0_BAUD_NORMAL (0 << 0)
3815 # define MR0_BAUD_EXT1 (1 << 0)
3816 # define MR0_BAUD_EXT2 (5 << 0)
3817 # define MR0_FIFO (1 << 3)
3818 # define MR0_TXLVL (1 << 4)
3819 # define MR1_BITS_5 (0 << 0)
3820 # define MR1_BITS_6 (1 << 0)
3821 # define MR1_BITS_7 (2 << 0)
3822 # define MR1_BITS_8 (3 << 0)
3823 # define MR1_PAR_EVN (0 << 2)
3824 # define MR1_PAR_ODD (1 << 2)
3825 # define MR1_PAR_NO (4 << 2)
3826 # define MR2_STOP1 (7 << 0)
3827 # define MR2_STOP2 (0xf << 0)
3828 #define SCCNXP_SR_REG (0x01)
3829 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3830 # define SR_RXRDY (1 << 0)
3831 # define SR_FULL (1 << 1)
3832 # define SR_TXRDY (1 << 2)
3833 # define SR_TXEMT (1 << 3)
3834 # define SR_OVR (1 << 4)
3835 # define SR_PE (1 << 5)
3836 # define SR_FE (1 << 6)
3837 # define SR_BRK (1 << 7)
3838 #define SCCNXP_CR_REG (0x02)
3839 # define CR_RX_ENABLE (1 << 0)
3840 # define CR_RX_DISABLE (1 << 1)
3841 # define CR_TX_ENABLE (1 << 2)
3842 # define CR_TX_DISABLE (1 << 3)
3843 # define CR_CMD_MRPTR1 (0x01 << 4)
3844 # define CR_CMD_RX_RESET (0x02 << 4)
3845 # define CR_CMD_TX_RESET (0x03 << 4)
3846 # define CR_CMD_STATUS_RESET (0x04 << 4)
3847 # define CR_CMD_BREAK_RESET (0x05 << 4)
3848 # define CR_CMD_START_BREAK (0x06 << 4)
3849 # define CR_CMD_STOP_BREAK (0x07 << 4)
3850 # define CR_CMD_MRPTR0 (0x0b << 4)
3851 #define SCCNXP_RHR_REG (0x03)
3852 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3853 #define SCCNXP_IPCR_REG (0x04)
3854 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3855 # define ACR_BAUD0 (0 << 7)
3856 # define ACR_BAUD1 (1 << 7)
3857 # define ACR_TIMER_MODE (6 << 4)
3858 #define SCCNXP_ISR_REG (0x05)
3859 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3860 # define IMR_TXRDY (1 << 0)
3861 # define IMR_RXRDY (1 << 1)
3862 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3863 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3864 #define SCCNXP_IPR_REG (0x0d)
3865 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3866 #define SCCNXP_SOP_REG (0x0e)
3867 #define SCCNXP_ROP_REG (0x0f)
3868 #define MCTRL_MASK(sig) (0xf << (sig))
3869 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3870 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3871 #define SCCNXP_HAVE_IO 0x00000001
3872 #define SCCNXP_HAVE_MR0 0x00000002
3873 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3874 #endif
3875 /* LDV_COMMENT_END_PREP */
3876 /* LDV_COMMENT_FUNCTION_CALL Function from field "verify_port" from driver structure with callbacks "sccnxp_ops" */
3877 ldv_handler_precall();
3878 sccnxp_verify_port( var_group1, var_group3);
3879 /* LDV_COMMENT_BEGIN_PREP */
3880 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3881 #endif
3882 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3883 #endif
3884 /* LDV_COMMENT_END_PREP */
3885
3886
3887
3888
3889 }
3890
3891 break;
3892 case 15: {
3893
3894 /** STRUCT: struct type: platform_driver, struct name: sccnxp_uart_driver **/
3895 if(ldv_s_sccnxp_uart_driver_platform_driver==0) {
3896
3897 /* content: static int sccnxp_probe(struct platform_device *pdev)*/
3898 /* LDV_COMMENT_BEGIN_PREP */
3899 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3900 #define SUPPORT_SYSRQ
3901 #endif
3902 #define SCCNXP_NAME "uart-sccnxp"
3903 #define SCCNXP_MAJOR 204
3904 #define SCCNXP_MINOR 205
3905 #define SCCNXP_MR_REG (0x00)
3906 # define MR0_BAUD_NORMAL (0 << 0)
3907 # define MR0_BAUD_EXT1 (1 << 0)
3908 # define MR0_BAUD_EXT2 (5 << 0)
3909 # define MR0_FIFO (1 << 3)
3910 # define MR0_TXLVL (1 << 4)
3911 # define MR1_BITS_5 (0 << 0)
3912 # define MR1_BITS_6 (1 << 0)
3913 # define MR1_BITS_7 (2 << 0)
3914 # define MR1_BITS_8 (3 << 0)
3915 # define MR1_PAR_EVN (0 << 2)
3916 # define MR1_PAR_ODD (1 << 2)
3917 # define MR1_PAR_NO (4 << 2)
3918 # define MR2_STOP1 (7 << 0)
3919 # define MR2_STOP2 (0xf << 0)
3920 #define SCCNXP_SR_REG (0x01)
3921 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3922 # define SR_RXRDY (1 << 0)
3923 # define SR_FULL (1 << 1)
3924 # define SR_TXRDY (1 << 2)
3925 # define SR_TXEMT (1 << 3)
3926 # define SR_OVR (1 << 4)
3927 # define SR_PE (1 << 5)
3928 # define SR_FE (1 << 6)
3929 # define SR_BRK (1 << 7)
3930 #define SCCNXP_CR_REG (0x02)
3931 # define CR_RX_ENABLE (1 << 0)
3932 # define CR_RX_DISABLE (1 << 1)
3933 # define CR_TX_ENABLE (1 << 2)
3934 # define CR_TX_DISABLE (1 << 3)
3935 # define CR_CMD_MRPTR1 (0x01 << 4)
3936 # define CR_CMD_RX_RESET (0x02 << 4)
3937 # define CR_CMD_TX_RESET (0x03 << 4)
3938 # define CR_CMD_STATUS_RESET (0x04 << 4)
3939 # define CR_CMD_BREAK_RESET (0x05 << 4)
3940 # define CR_CMD_START_BREAK (0x06 << 4)
3941 # define CR_CMD_STOP_BREAK (0x07 << 4)
3942 # define CR_CMD_MRPTR0 (0x0b << 4)
3943 #define SCCNXP_RHR_REG (0x03)
3944 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3945 #define SCCNXP_IPCR_REG (0x04)
3946 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3947 # define ACR_BAUD0 (0 << 7)
3948 # define ACR_BAUD1 (1 << 7)
3949 # define ACR_TIMER_MODE (6 << 4)
3950 #define SCCNXP_ISR_REG (0x05)
3951 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3952 # define IMR_TXRDY (1 << 0)
3953 # define IMR_RXRDY (1 << 1)
3954 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3955 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3956 #define SCCNXP_IPR_REG (0x0d)
3957 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3958 #define SCCNXP_SOP_REG (0x0e)
3959 #define SCCNXP_ROP_REG (0x0f)
3960 #define MCTRL_MASK(sig) (0xf << (sig))
3961 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3962 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3963 #define SCCNXP_HAVE_IO 0x00000001
3964 #define SCCNXP_HAVE_MR0 0x00000002
3965 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3966 #endif
3967 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3968 #endif
3969 /* LDV_COMMENT_END_PREP */
3970 /* LDV_COMMENT_FUNCTION_CALL Function from field "probe" from driver structure with callbacks "sccnxp_uart_driver". Standart function test for correct return result. */
3971 res_sccnxp_probe_32 = sccnxp_probe( var_group4);
3972 ldv_check_return_value(res_sccnxp_probe_32);
3973 ldv_check_return_value_probe(res_sccnxp_probe_32);
3974 if(res_sccnxp_probe_32)
3975 goto ldv_module_exit;
3976 ldv_s_sccnxp_uart_driver_platform_driver++;
3977
3978 }
3979
3980 }
3981
3982 break;
3983 case 16: {
3984
3985 /** STRUCT: struct type: platform_driver, struct name: sccnxp_uart_driver **/
3986 if(ldv_s_sccnxp_uart_driver_platform_driver==1) {
3987
3988 /* content: static int sccnxp_remove(struct platform_device *pdev)*/
3989 /* LDV_COMMENT_BEGIN_PREP */
3990 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3991 #define SUPPORT_SYSRQ
3992 #endif
3993 #define SCCNXP_NAME "uart-sccnxp"
3994 #define SCCNXP_MAJOR 204
3995 #define SCCNXP_MINOR 205
3996 #define SCCNXP_MR_REG (0x00)
3997 # define MR0_BAUD_NORMAL (0 << 0)
3998 # define MR0_BAUD_EXT1 (1 << 0)
3999 # define MR0_BAUD_EXT2 (5 << 0)
4000 # define MR0_FIFO (1 << 3)
4001 # define MR0_TXLVL (1 << 4)
4002 # define MR1_BITS_5 (0 << 0)
4003 # define MR1_BITS_6 (1 << 0)
4004 # define MR1_BITS_7 (2 << 0)
4005 # define MR1_BITS_8 (3 << 0)
4006 # define MR1_PAR_EVN (0 << 2)
4007 # define MR1_PAR_ODD (1 << 2)
4008 # define MR1_PAR_NO (4 << 2)
4009 # define MR2_STOP1 (7 << 0)
4010 # define MR2_STOP2 (0xf << 0)
4011 #define SCCNXP_SR_REG (0x01)
4012 #define SCCNXP_CSR_REG SCCNXP_SR_REG
4013 # define SR_RXRDY (1 << 0)
4014 # define SR_FULL (1 << 1)
4015 # define SR_TXRDY (1 << 2)
4016 # define SR_TXEMT (1 << 3)
4017 # define SR_OVR (1 << 4)
4018 # define SR_PE (1 << 5)
4019 # define SR_FE (1 << 6)
4020 # define SR_BRK (1 << 7)
4021 #define SCCNXP_CR_REG (0x02)
4022 # define CR_RX_ENABLE (1 << 0)
4023 # define CR_RX_DISABLE (1 << 1)
4024 # define CR_TX_ENABLE (1 << 2)
4025 # define CR_TX_DISABLE (1 << 3)
4026 # define CR_CMD_MRPTR1 (0x01 << 4)
4027 # define CR_CMD_RX_RESET (0x02 << 4)
4028 # define CR_CMD_TX_RESET (0x03 << 4)
4029 # define CR_CMD_STATUS_RESET (0x04 << 4)
4030 # define CR_CMD_BREAK_RESET (0x05 << 4)
4031 # define CR_CMD_START_BREAK (0x06 << 4)
4032 # define CR_CMD_STOP_BREAK (0x07 << 4)
4033 # define CR_CMD_MRPTR0 (0x0b << 4)
4034 #define SCCNXP_RHR_REG (0x03)
4035 #define SCCNXP_THR_REG SCCNXP_RHR_REG
4036 #define SCCNXP_IPCR_REG (0x04)
4037 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
4038 # define ACR_BAUD0 (0 << 7)
4039 # define ACR_BAUD1 (1 << 7)
4040 # define ACR_TIMER_MODE (6 << 4)
4041 #define SCCNXP_ISR_REG (0x05)
4042 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
4043 # define IMR_TXRDY (1 << 0)
4044 # define IMR_RXRDY (1 << 1)
4045 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
4046 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
4047 #define SCCNXP_IPR_REG (0x0d)
4048 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
4049 #define SCCNXP_SOP_REG (0x0e)
4050 #define SCCNXP_ROP_REG (0x0f)
4051 #define MCTRL_MASK(sig) (0xf << (sig))
4052 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
4053 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
4054 #define SCCNXP_HAVE_IO 0x00000001
4055 #define SCCNXP_HAVE_MR0 0x00000002
4056 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4057 #endif
4058 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4059 #endif
4060 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4061 #endif
4062 /* LDV_COMMENT_END_PREP */
4063 /* LDV_COMMENT_FUNCTION_CALL Function from field "remove" from driver structure with callbacks "sccnxp_uart_driver" */
4064 ldv_handler_precall();
4065 sccnxp_remove( var_group4);
4066 ldv_s_sccnxp_uart_driver_platform_driver=0;
4067
4068 }
4069
4070 }
4071
4072 break;
4073 case 17: {
4074
4075 /** CALLBACK SECTION request_irq **/
4076 LDV_IN_INTERRUPT=2;
4077
4078 /* content: static irqreturn_t sccnxp_ist(int irq, void *dev_id)*/
4079 /* LDV_COMMENT_BEGIN_PREP */
4080 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
4081 #define SUPPORT_SYSRQ
4082 #endif
4083 #define SCCNXP_NAME "uart-sccnxp"
4084 #define SCCNXP_MAJOR 204
4085 #define SCCNXP_MINOR 205
4086 #define SCCNXP_MR_REG (0x00)
4087 # define MR0_BAUD_NORMAL (0 << 0)
4088 # define MR0_BAUD_EXT1 (1 << 0)
4089 # define MR0_BAUD_EXT2 (5 << 0)
4090 # define MR0_FIFO (1 << 3)
4091 # define MR0_TXLVL (1 << 4)
4092 # define MR1_BITS_5 (0 << 0)
4093 # define MR1_BITS_6 (1 << 0)
4094 # define MR1_BITS_7 (2 << 0)
4095 # define MR1_BITS_8 (3 << 0)
4096 # define MR1_PAR_EVN (0 << 2)
4097 # define MR1_PAR_ODD (1 << 2)
4098 # define MR1_PAR_NO (4 << 2)
4099 # define MR2_STOP1 (7 << 0)
4100 # define MR2_STOP2 (0xf << 0)
4101 #define SCCNXP_SR_REG (0x01)
4102 #define SCCNXP_CSR_REG SCCNXP_SR_REG
4103 # define SR_RXRDY (1 << 0)
4104 # define SR_FULL (1 << 1)
4105 # define SR_TXRDY (1 << 2)
4106 # define SR_TXEMT (1 << 3)
4107 # define SR_OVR (1 << 4)
4108 # define SR_PE (1 << 5)
4109 # define SR_FE (1 << 6)
4110 # define SR_BRK (1 << 7)
4111 #define SCCNXP_CR_REG (0x02)
4112 # define CR_RX_ENABLE (1 << 0)
4113 # define CR_RX_DISABLE (1 << 1)
4114 # define CR_TX_ENABLE (1 << 2)
4115 # define CR_TX_DISABLE (1 << 3)
4116 # define CR_CMD_MRPTR1 (0x01 << 4)
4117 # define CR_CMD_RX_RESET (0x02 << 4)
4118 # define CR_CMD_TX_RESET (0x03 << 4)
4119 # define CR_CMD_STATUS_RESET (0x04 << 4)
4120 # define CR_CMD_BREAK_RESET (0x05 << 4)
4121 # define CR_CMD_START_BREAK (0x06 << 4)
4122 # define CR_CMD_STOP_BREAK (0x07 << 4)
4123 # define CR_CMD_MRPTR0 (0x0b << 4)
4124 #define SCCNXP_RHR_REG (0x03)
4125 #define SCCNXP_THR_REG SCCNXP_RHR_REG
4126 #define SCCNXP_IPCR_REG (0x04)
4127 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
4128 # define ACR_BAUD0 (0 << 7)
4129 # define ACR_BAUD1 (1 << 7)
4130 # define ACR_TIMER_MODE (6 << 4)
4131 #define SCCNXP_ISR_REG (0x05)
4132 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
4133 # define IMR_TXRDY (1 << 0)
4134 # define IMR_RXRDY (1 << 1)
4135 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
4136 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
4137 #define SCCNXP_IPR_REG (0x0d)
4138 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
4139 #define SCCNXP_SOP_REG (0x0e)
4140 #define SCCNXP_ROP_REG (0x0f)
4141 #define MCTRL_MASK(sig) (0xf << (sig))
4142 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
4143 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
4144 #define SCCNXP_HAVE_IO 0x00000001
4145 #define SCCNXP_HAVE_MR0 0x00000002
4146 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4147 #endif
4148 /* LDV_COMMENT_END_PREP */
4149 /* LDV_COMMENT_FUNCTION_CALL */
4150 ldv_handler_precall();
4151 sccnxp_ist( var_sccnxp_ist_13_p0, var_sccnxp_ist_13_p1);
4152 /* LDV_COMMENT_BEGIN_PREP */
4153 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4154 #endif
4155 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4156 #endif
4157 /* LDV_COMMENT_END_PREP */
4158 LDV_IN_INTERRUPT=1;
4159
4160
4161
4162 }
4163
4164 break;
4165 default: break;
4166
4167 }
4168
4169 }
4170
4171 ldv_module_exit:
4172
4173 /* LDV_COMMENT_FUNCTION_CALL Checks that all resources and locks are correctly released before the driver will be unloaded. */
4174 ldv_final: ldv_check_final_state();
4175
4176 /* LDV_COMMENT_END_FUNCTION_CALL_SECTION */
4177 return;
4178
4179 }
4180 #endif
4181
4182 /* LDV_COMMENT_END_MAIN */ 1
2 #include <linux/kernel.h>
3 bool ldv_is_err(const void *ptr);
4 bool ldv_is_err_or_null(const void *ptr);
5 void* ldv_err_ptr(long error);
6 long ldv_ptr_err(const void *ptr);
7
8 #include <linux/module.h>
9 struct clk;
10
11 extern void ldv_clk_disable_clk(struct clk *clk);
12 extern int ldv_clk_enable_clk(void);
13 #line 1 "/work/ldvuser/ref_launch/work/current--X--.--X--defaultlinux-4.13-rc1--X--320_7a--X--cpachecker/linux-4.13-rc1/csd_deg_dscv/4872/dscv_tempdir/dscv/ri/320_7a/drivers/tty/serial/sccnxp.c"
14
15 /*
16 * NXP (Philips) SCC+++(SCN+++) serial driver
17 *
18 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
19 *
20 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 */
27
28 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
29 #define SUPPORT_SYSRQ
30 #endif
31
32 #include <linux/clk.h>
33 #include <linux/err.h>
34 #include <linux/module.h>
35 #include <linux/device.h>
36 #include <linux/console.h>
37 #include <linux/serial_core.h>
38 #include <linux/serial.h>
39 #include <linux/io.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/platform_data/serial-sccnxp.h>
45 #include <linux/regulator/consumer.h>
46
47 #define SCCNXP_NAME "uart-sccnxp"
48 #define SCCNXP_MAJOR 204
49 #define SCCNXP_MINOR 205
50
51 #define SCCNXP_MR_REG (0x00)
52 # define MR0_BAUD_NORMAL (0 << 0)
53 # define MR0_BAUD_EXT1 (1 << 0)
54 # define MR0_BAUD_EXT2 (5 << 0)
55 # define MR0_FIFO (1 << 3)
56 # define MR0_TXLVL (1 << 4)
57 # define MR1_BITS_5 (0 << 0)
58 # define MR1_BITS_6 (1 << 0)
59 # define MR1_BITS_7 (2 << 0)
60 # define MR1_BITS_8 (3 << 0)
61 # define MR1_PAR_EVN (0 << 2)
62 # define MR1_PAR_ODD (1 << 2)
63 # define MR1_PAR_NO (4 << 2)
64 # define MR2_STOP1 (7 << 0)
65 # define MR2_STOP2 (0xf << 0)
66 #define SCCNXP_SR_REG (0x01)
67 #define SCCNXP_CSR_REG SCCNXP_SR_REG
68 # define SR_RXRDY (1 << 0)
69 # define SR_FULL (1 << 1)
70 # define SR_TXRDY (1 << 2)
71 # define SR_TXEMT (1 << 3)
72 # define SR_OVR (1 << 4)
73 # define SR_PE (1 << 5)
74 # define SR_FE (1 << 6)
75 # define SR_BRK (1 << 7)
76 #define SCCNXP_CR_REG (0x02)
77 # define CR_RX_ENABLE (1 << 0)
78 # define CR_RX_DISABLE (1 << 1)
79 # define CR_TX_ENABLE (1 << 2)
80 # define CR_TX_DISABLE (1 << 3)
81 # define CR_CMD_MRPTR1 (0x01 << 4)
82 # define CR_CMD_RX_RESET (0x02 << 4)
83 # define CR_CMD_TX_RESET (0x03 << 4)
84 # define CR_CMD_STATUS_RESET (0x04 << 4)
85 # define CR_CMD_BREAK_RESET (0x05 << 4)
86 # define CR_CMD_START_BREAK (0x06 << 4)
87 # define CR_CMD_STOP_BREAK (0x07 << 4)
88 # define CR_CMD_MRPTR0 (0x0b << 4)
89 #define SCCNXP_RHR_REG (0x03)
90 #define SCCNXP_THR_REG SCCNXP_RHR_REG
91 #define SCCNXP_IPCR_REG (0x04)
92 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
93 # define ACR_BAUD0 (0 << 7)
94 # define ACR_BAUD1 (1 << 7)
95 # define ACR_TIMER_MODE (6 << 4)
96 #define SCCNXP_ISR_REG (0x05)
97 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
98 # define IMR_TXRDY (1 << 0)
99 # define IMR_RXRDY (1 << 1)
100 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
101 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
102 #define SCCNXP_IPR_REG (0x0d)
103 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
104 #define SCCNXP_SOP_REG (0x0e)
105 #define SCCNXP_ROP_REG (0x0f)
106
107 /* Route helpers */
108 #define MCTRL_MASK(sig) (0xf << (sig))
109 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
110 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
111
112 #define SCCNXP_HAVE_IO 0x00000001
113 #define SCCNXP_HAVE_MR0 0x00000002
114
115 struct sccnxp_chip {
116 const char *name;
117 unsigned int nr;
118 unsigned long freq_min;
119 unsigned long freq_std;
120 unsigned long freq_max;
121 unsigned int flags;
122 unsigned int fifosize;
123 };
124
125 struct sccnxp_port {
126 struct uart_driver uart;
127 struct uart_port port[SCCNXP_MAX_UARTS];
128 bool opened[SCCNXP_MAX_UARTS];
129
130 int irq;
131 u8 imr;
132
133 struct sccnxp_chip *chip;
134
135 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
136 struct console console;
137 #endif
138
139 spinlock_t lock;
140
141 bool poll;
142 struct timer_list timer;
143
144 struct sccnxp_pdata pdata;
145
146 struct regulator *regulator;
147 };
148
149 static const struct sccnxp_chip sc2681 = {
150 .name = "SC2681",
151 .nr = 2,
152 .freq_min = 1000000,
153 .freq_std = 3686400,
154 .freq_max = 4000000,
155 .flags = SCCNXP_HAVE_IO,
156 .fifosize = 3,
157 };
158
159 static const struct sccnxp_chip sc2691 = {
160 .name = "SC2691",
161 .nr = 1,
162 .freq_min = 1000000,
163 .freq_std = 3686400,
164 .freq_max = 4000000,
165 .flags = 0,
166 .fifosize = 3,
167 };
168
169 static const struct sccnxp_chip sc2692 = {
170 .name = "SC2692",
171 .nr = 2,
172 .freq_min = 1000000,
173 .freq_std = 3686400,
174 .freq_max = 4000000,
175 .flags = SCCNXP_HAVE_IO,
176 .fifosize = 3,
177 };
178
179 static const struct sccnxp_chip sc2891 = {
180 .name = "SC2891",
181 .nr = 1,
182 .freq_min = 100000,
183 .freq_std = 3686400,
184 .freq_max = 8000000,
185 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
186 .fifosize = 16,
187 };
188
189 static const struct sccnxp_chip sc2892 = {
190 .name = "SC2892",
191 .nr = 2,
192 .freq_min = 100000,
193 .freq_std = 3686400,
194 .freq_max = 8000000,
195 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
196 .fifosize = 16,
197 };
198
199 static const struct sccnxp_chip sc28202 = {
200 .name = "SC28202",
201 .nr = 2,
202 .freq_min = 1000000,
203 .freq_std = 14745600,
204 .freq_max = 50000000,
205 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
206 .fifosize = 256,
207 };
208
209 static const struct sccnxp_chip sc68681 = {
210 .name = "SC68681",
211 .nr = 2,
212 .freq_min = 1000000,
213 .freq_std = 3686400,
214 .freq_max = 4000000,
215 .flags = SCCNXP_HAVE_IO,
216 .fifosize = 3,
217 };
218
219 static const struct sccnxp_chip sc68692 = {
220 .name = "SC68692",
221 .nr = 2,
222 .freq_min = 1000000,
223 .freq_std = 3686400,
224 .freq_max = 4000000,
225 .flags = SCCNXP_HAVE_IO,
226 .fifosize = 3,
227 };
228
229 static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
230 {
231 return readb(port->membase + (reg << port->regshift));
232 }
233
234 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
235 {
236 writeb(v, port->membase + (reg << port->regshift));
237 }
238
239 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
240 {
241 return sccnxp_read(port, (port->line << 3) + reg);
242 }
243
244 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
245 {
246 sccnxp_write(port, (port->line << 3) + reg, v);
247 }
248
249 static int sccnxp_update_best_err(int a, int b, int *besterr)
250 {
251 int err = abs(a - b);
252
253 if ((*besterr < 0) || (*besterr > err)) {
254 *besterr = err;
255 return 0;
256 }
257
258 return 1;
259 }
260
261 static const struct {
262 u8 csr;
263 u8 acr;
264 u8 mr0;
265 int baud;
266 } baud_std[] = {
267 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
268 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
269 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
270 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
271 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
272 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
273 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
274 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
275 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
276 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
277 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
278 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
279 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
280 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
281 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
282 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
283 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
284 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
285 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
286 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
287 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
288 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
289 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
290 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
291 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
292 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
293 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
294 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
295 { 0, 0, 0, 0 }
296 };
297
298 static int sccnxp_set_baud(struct uart_port *port, int baud)
299 {
300 struct sccnxp_port *s = dev_get_drvdata(port->dev);
301 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
302 struct sccnxp_chip *chip = s->chip;
303 u8 i, acr = 0, csr = 0, mr0 = 0;
304
305 /* Find best baud from table */
306 for (i = 0; baud_std[i].baud && besterr; i++) {
307 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
308 continue;
309 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
310 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
311 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
312 acr = baud_std[i].acr;
313 csr = baud_std[i].csr;
314 mr0 = baud_std[i].mr0;
315 bestbaud = tmp_baud;
316 }
317 }
318
319 if (chip->flags & SCCNXP_HAVE_MR0) {
320 /* Enable FIFO, set half level for TX */
321 mr0 |= MR0_FIFO | MR0_TXLVL;
322 /* Update MR0 */
323 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
324 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
325 }
326
327 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
328 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
329
330 if (baud != bestbaud)
331 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
332 baud, bestbaud);
333
334 return bestbaud;
335 }
336
337 static void sccnxp_enable_irq(struct uart_port *port, int mask)
338 {
339 struct sccnxp_port *s = dev_get_drvdata(port->dev);
340
341 s->imr |= mask << (port->line * 4);
342 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
343 }
344
345 static void sccnxp_disable_irq(struct uart_port *port, int mask)
346 {
347 struct sccnxp_port *s = dev_get_drvdata(port->dev);
348
349 s->imr &= ~(mask << (port->line * 4));
350 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
351 }
352
353 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
354 {
355 u8 bitmask;
356 struct sccnxp_port *s = dev_get_drvdata(port->dev);
357
358 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
359 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
360 if (state)
361 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
362 else
363 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
364 }
365 }
366
367 static void sccnxp_handle_rx(struct uart_port *port)
368 {
369 u8 sr;
370 unsigned int ch, flag;
371
372 for (;;) {
373 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
374 if (!(sr & SR_RXRDY))
375 break;
376 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
377
378 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
379
380 port->icount.rx++;
381 flag = TTY_NORMAL;
382
383 if (unlikely(sr)) {
384 if (sr & SR_BRK) {
385 port->icount.brk++;
386 sccnxp_port_write(port, SCCNXP_CR_REG,
387 CR_CMD_BREAK_RESET);
388 if (uart_handle_break(port))
389 continue;
390 } else if (sr & SR_PE)
391 port->icount.parity++;
392 else if (sr & SR_FE)
393 port->icount.frame++;
394 else if (sr & SR_OVR) {
395 port->icount.overrun++;
396 sccnxp_port_write(port, SCCNXP_CR_REG,
397 CR_CMD_STATUS_RESET);
398 }
399
400 sr &= port->read_status_mask;
401 if (sr & SR_BRK)
402 flag = TTY_BREAK;
403 else if (sr & SR_PE)
404 flag = TTY_PARITY;
405 else if (sr & SR_FE)
406 flag = TTY_FRAME;
407 else if (sr & SR_OVR)
408 flag = TTY_OVERRUN;
409 }
410
411 if (uart_handle_sysrq_char(port, ch))
412 continue;
413
414 if (sr & port->ignore_status_mask)
415 continue;
416
417 uart_insert_char(port, sr, SR_OVR, ch, flag);
418 }
419
420 tty_flip_buffer_push(&port->state->port);
421 }
422
423 static void sccnxp_handle_tx(struct uart_port *port)
424 {
425 u8 sr;
426 struct circ_buf *xmit = &port->state->xmit;
427 struct sccnxp_port *s = dev_get_drvdata(port->dev);
428
429 if (unlikely(port->x_char)) {
430 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
431 port->icount.tx++;
432 port->x_char = 0;
433 return;
434 }
435
436 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
437 /* Disable TX if FIFO is empty */
438 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
439 sccnxp_disable_irq(port, IMR_TXRDY);
440
441 /* Set direction to input */
442 if (s->chip->flags & SCCNXP_HAVE_IO)
443 sccnxp_set_bit(port, DIR_OP, 0);
444 }
445 return;
446 }
447
448 while (!uart_circ_empty(xmit)) {
449 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
450 if (!(sr & SR_TXRDY))
451 break;
452
453 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
454 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
455 port->icount.tx++;
456 }
457
458 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
459 uart_write_wakeup(port);
460 }
461
462 static void sccnxp_handle_events(struct sccnxp_port *s)
463 {
464 int i;
465 u8 isr;
466
467 do {
468 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
469 isr &= s->imr;
470 if (!isr)
471 break;
472
473 for (i = 0; i < s->uart.nr; i++) {
474 if (s->opened[i] && (isr & ISR_RXRDY(i)))
475 sccnxp_handle_rx(&s->port[i]);
476 if (s->opened[i] && (isr & ISR_TXRDY(i)))
477 sccnxp_handle_tx(&s->port[i]);
478 }
479 } while (1);
480 }
481
482 static void sccnxp_timer(unsigned long data)
483 {
484 struct sccnxp_port *s = (struct sccnxp_port *)data;
485 unsigned long flags;
486
487 spin_lock_irqsave(&s->lock, flags);
488 sccnxp_handle_events(s);
489 spin_unlock_irqrestore(&s->lock, flags);
490
491 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
492 }
493
494 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
495 {
496 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
497 unsigned long flags;
498
499 spin_lock_irqsave(&s->lock, flags);
500 sccnxp_handle_events(s);
501 spin_unlock_irqrestore(&s->lock, flags);
502
503 return IRQ_HANDLED;
504 }
505
506 static void sccnxp_start_tx(struct uart_port *port)
507 {
508 struct sccnxp_port *s = dev_get_drvdata(port->dev);
509 unsigned long flags;
510
511 spin_lock_irqsave(&s->lock, flags);
512
513 /* Set direction to output */
514 if (s->chip->flags & SCCNXP_HAVE_IO)
515 sccnxp_set_bit(port, DIR_OP, 1);
516
517 sccnxp_enable_irq(port, IMR_TXRDY);
518
519 spin_unlock_irqrestore(&s->lock, flags);
520 }
521
522 static void sccnxp_stop_tx(struct uart_port *port)
523 {
524 /* Do nothing */
525 }
526
527 static void sccnxp_stop_rx(struct uart_port *port)
528 {
529 struct sccnxp_port *s = dev_get_drvdata(port->dev);
530 unsigned long flags;
531
532 spin_lock_irqsave(&s->lock, flags);
533 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
534 spin_unlock_irqrestore(&s->lock, flags);
535 }
536
537 static unsigned int sccnxp_tx_empty(struct uart_port *port)
538 {
539 u8 val;
540 unsigned long flags;
541 struct sccnxp_port *s = dev_get_drvdata(port->dev);
542
543 spin_lock_irqsave(&s->lock, flags);
544 val = sccnxp_port_read(port, SCCNXP_SR_REG);
545 spin_unlock_irqrestore(&s->lock, flags);
546
547 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
548 }
549
550 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
551 {
552 struct sccnxp_port *s = dev_get_drvdata(port->dev);
553 unsigned long flags;
554
555 if (!(s->chip->flags & SCCNXP_HAVE_IO))
556 return;
557
558 spin_lock_irqsave(&s->lock, flags);
559
560 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
561 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
562
563 spin_unlock_irqrestore(&s->lock, flags);
564 }
565
566 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
567 {
568 u8 bitmask, ipr;
569 unsigned long flags;
570 struct sccnxp_port *s = dev_get_drvdata(port->dev);
571 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
572
573 if (!(s->chip->flags & SCCNXP_HAVE_IO))
574 return mctrl;
575
576 spin_lock_irqsave(&s->lock, flags);
577
578 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
579
580 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
581 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
582 DSR_IP);
583 mctrl &= ~TIOCM_DSR;
584 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
585 }
586 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
587 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
588 CTS_IP);
589 mctrl &= ~TIOCM_CTS;
590 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
591 }
592 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
593 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
594 DCD_IP);
595 mctrl &= ~TIOCM_CAR;
596 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
597 }
598 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
599 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
600 RNG_IP);
601 mctrl &= ~TIOCM_RNG;
602 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
603 }
604
605 spin_unlock_irqrestore(&s->lock, flags);
606
607 return mctrl;
608 }
609
610 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
611 {
612 struct sccnxp_port *s = dev_get_drvdata(port->dev);
613 unsigned long flags;
614
615 spin_lock_irqsave(&s->lock, flags);
616 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
617 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
618 spin_unlock_irqrestore(&s->lock, flags);
619 }
620
621 static void sccnxp_set_termios(struct uart_port *port,
622 struct ktermios *termios, struct ktermios *old)
623 {
624 struct sccnxp_port *s = dev_get_drvdata(port->dev);
625 unsigned long flags;
626 u8 mr1, mr2;
627 int baud;
628
629 spin_lock_irqsave(&s->lock, flags);
630
631 /* Mask termios capabilities we don't support */
632 termios->c_cflag &= ~CMSPAR;
633
634 /* Disable RX & TX, reset break condition, status and FIFOs */
635 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
636 CR_RX_DISABLE | CR_TX_DISABLE);
637 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
638 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
639 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
640
641 /* Word size */
642 switch (termios->c_cflag & CSIZE) {
643 case CS5:
644 mr1 = MR1_BITS_5;
645 break;
646 case CS6:
647 mr1 = MR1_BITS_6;
648 break;
649 case CS7:
650 mr1 = MR1_BITS_7;
651 break;
652 case CS8:
653 default:
654 mr1 = MR1_BITS_8;
655 break;
656 }
657
658 /* Parity */
659 if (termios->c_cflag & PARENB) {
660 if (termios->c_cflag & PARODD)
661 mr1 |= MR1_PAR_ODD;
662 } else
663 mr1 |= MR1_PAR_NO;
664
665 /* Stop bits */
666 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
667
668 /* Update desired format */
669 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
670 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
671 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
672
673 /* Set read status mask */
674 port->read_status_mask = SR_OVR;
675 if (termios->c_iflag & INPCK)
676 port->read_status_mask |= SR_PE | SR_FE;
677 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
678 port->read_status_mask |= SR_BRK;
679
680 /* Set status ignore mask */
681 port->ignore_status_mask = 0;
682 if (termios->c_iflag & IGNBRK)
683 port->ignore_status_mask |= SR_BRK;
684 if (termios->c_iflag & IGNPAR)
685 port->ignore_status_mask |= SR_PE;
686 if (!(termios->c_cflag & CREAD))
687 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
688
689 /* Setup baudrate */
690 baud = uart_get_baud_rate(port, termios, old, 50,
691 (s->chip->flags & SCCNXP_HAVE_MR0) ?
692 230400 : 38400);
693 baud = sccnxp_set_baud(port, baud);
694
695 /* Update timeout according to new baud rate */
696 uart_update_timeout(port, termios->c_cflag, baud);
697
698 /* Report actual baudrate back to core */
699 if (tty_termios_baud_rate(termios))
700 tty_termios_encode_baud_rate(termios, baud, baud);
701
702 /* Enable RX & TX */
703 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
704
705 spin_unlock_irqrestore(&s->lock, flags);
706 }
707
708 static int sccnxp_startup(struct uart_port *port)
709 {
710 struct sccnxp_port *s = dev_get_drvdata(port->dev);
711 unsigned long flags;
712
713 spin_lock_irqsave(&s->lock, flags);
714
715 if (s->chip->flags & SCCNXP_HAVE_IO) {
716 /* Outputs are controlled manually */
717 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
718 }
719
720 /* Reset break condition, status and FIFOs */
721 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
722 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
723 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
724 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
725
726 /* Enable RX & TX */
727 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
728
729 /* Enable RX interrupt */
730 sccnxp_enable_irq(port, IMR_RXRDY);
731
732 s->opened[port->line] = 1;
733
734 spin_unlock_irqrestore(&s->lock, flags);
735
736 return 0;
737 }
738
739 static void sccnxp_shutdown(struct uart_port *port)
740 {
741 struct sccnxp_port *s = dev_get_drvdata(port->dev);
742 unsigned long flags;
743
744 spin_lock_irqsave(&s->lock, flags);
745
746 s->opened[port->line] = 0;
747
748 /* Disable interrupts */
749 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
750
751 /* Disable TX & RX */
752 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
753
754 /* Leave direction to input */
755 if (s->chip->flags & SCCNXP_HAVE_IO)
756 sccnxp_set_bit(port, DIR_OP, 0);
757
758 spin_unlock_irqrestore(&s->lock, flags);
759 }
760
761 static const char *sccnxp_type(struct uart_port *port)
762 {
763 struct sccnxp_port *s = dev_get_drvdata(port->dev);
764
765 return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
766 }
767
768 static void sccnxp_release_port(struct uart_port *port)
769 {
770 /* Do nothing */
771 }
772
773 static int sccnxp_request_port(struct uart_port *port)
774 {
775 /* Do nothing */
776 return 0;
777 }
778
779 static void sccnxp_config_port(struct uart_port *port, int flags)
780 {
781 if (flags & UART_CONFIG_TYPE)
782 port->type = PORT_SC26XX;
783 }
784
785 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
786 {
787 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
788 return 0;
789 if (s->irq == port->irq)
790 return 0;
791
792 return -EINVAL;
793 }
794
795 static const struct uart_ops sccnxp_ops = {
796 .tx_empty = sccnxp_tx_empty,
797 .set_mctrl = sccnxp_set_mctrl,
798 .get_mctrl = sccnxp_get_mctrl,
799 .stop_tx = sccnxp_stop_tx,
800 .start_tx = sccnxp_start_tx,
801 .stop_rx = sccnxp_stop_rx,
802 .break_ctl = sccnxp_break_ctl,
803 .startup = sccnxp_startup,
804 .shutdown = sccnxp_shutdown,
805 .set_termios = sccnxp_set_termios,
806 .type = sccnxp_type,
807 .release_port = sccnxp_release_port,
808 .request_port = sccnxp_request_port,
809 .config_port = sccnxp_config_port,
810 .verify_port = sccnxp_verify_port,
811 };
812
813 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
814 static void sccnxp_console_putchar(struct uart_port *port, int c)
815 {
816 int tryes = 100000;
817
818 while (tryes--) {
819 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
820 sccnxp_port_write(port, SCCNXP_THR_REG, c);
821 break;
822 }
823 barrier();
824 }
825 }
826
827 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
828 {
829 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
830 struct uart_port *port = &s->port[co->index];
831 unsigned long flags;
832
833 spin_lock_irqsave(&s->lock, flags);
834 uart_console_write(port, c, n, sccnxp_console_putchar);
835 spin_unlock_irqrestore(&s->lock, flags);
836 }
837
838 static int sccnxp_console_setup(struct console *co, char *options)
839 {
840 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
841 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
842 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
843
844 if (options)
845 uart_parse_options(options, &baud, &parity, &bits, &flow);
846
847 return uart_set_options(port, co, baud, parity, bits, flow);
848 }
849 #endif
850
851 static const struct platform_device_id sccnxp_id_table[] = {
852 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },
853 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },
854 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },
855 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },
856 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },
857 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, },
858 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, },
859 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, },
860 { }
861 };
862 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
863
864 static int sccnxp_probe(struct platform_device *pdev)
865 {
866 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
867 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
868 int i, ret, uartclk;
869 struct sccnxp_port *s;
870 void __iomem *membase;
871 struct clk *clk;
872
873 membase = devm_ioremap_resource(&pdev->dev, res);
874 if (IS_ERR(membase))
875 return PTR_ERR(membase);
876
877 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
878 if (!s) {
879 dev_err(&pdev->dev, "Error allocating port structure\n");
880 return -ENOMEM;
881 }
882 platform_set_drvdata(pdev, s);
883
884 spin_lock_init(&s->lock);
885
886 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
887
888 s->regulator = devm_regulator_get(&pdev->dev, "vcc");
889 if (!IS_ERR(s->regulator)) {
890 ret = regulator_enable(s->regulator);
891 if (ret) {
892 dev_err(&pdev->dev,
893 "Failed to enable regulator: %i\n", ret);
894 return ret;
895 }
896 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
897 return -EPROBE_DEFER;
898
899 clk = devm_clk_get(&pdev->dev, NULL);
900 if (IS_ERR(clk)) {
901 ret = PTR_ERR(clk);
902 if (ret == -EPROBE_DEFER)
903 goto err_out;
904 uartclk = 0;
905 } else {
906 clk_prepare_enable(clk);
907 uartclk = clk_get_rate(clk);
908 }
909
910 if (!uartclk) {
911 dev_notice(&pdev->dev, "Using default clock frequency\n");
912 uartclk = s->chip->freq_std;
913 }
914
915 /* Check input frequency */
916 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
917 dev_err(&pdev->dev, "Frequency out of bounds\n");
918 ret = -EINVAL;
919 goto err_out;
920 }
921
922 if (pdata)
923 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
924
925 if (s->pdata.poll_time_us) {
926 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
927 s->pdata.poll_time_us);
928 s->poll = 1;
929 }
930
931 if (!s->poll) {
932 s->irq = platform_get_irq(pdev, 0);
933 if (s->irq < 0) {
934 dev_err(&pdev->dev, "Missing irq resource data\n");
935 ret = -ENXIO;
936 goto err_out;
937 }
938 }
939
940 s->uart.owner = THIS_MODULE;
941 s->uart.dev_name = "ttySC";
942 s->uart.major = SCCNXP_MAJOR;
943 s->uart.minor = SCCNXP_MINOR;
944 s->uart.nr = s->chip->nr;
945 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
946 s->uart.cons = &s->console;
947 s->uart.cons->device = uart_console_device;
948 s->uart.cons->write = sccnxp_console_write;
949 s->uart.cons->setup = sccnxp_console_setup;
950 s->uart.cons->flags = CON_PRINTBUFFER;
951 s->uart.cons->index = -1;
952 s->uart.cons->data = s;
953 strcpy(s->uart.cons->name, "ttySC");
954 #endif
955 ret = uart_register_driver(&s->uart);
956 if (ret) {
957 dev_err(&pdev->dev, "Registering UART driver failed\n");
958 goto err_out;
959 }
960
961 for (i = 0; i < s->uart.nr; i++) {
962 s->port[i].line = i;
963 s->port[i].dev = &pdev->dev;
964 s->port[i].irq = s->irq;
965 s->port[i].type = PORT_SC26XX;
966 s->port[i].fifosize = s->chip->fifosize;
967 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
968 s->port[i].iotype = UPIO_MEM;
969 s->port[i].mapbase = res->start;
970 s->port[i].membase = membase;
971 s->port[i].regshift = s->pdata.reg_shift;
972 s->port[i].uartclk = uartclk;
973 s->port[i].ops = &sccnxp_ops;
974 uart_add_one_port(&s->uart, &s->port[i]);
975 /* Set direction to input */
976 if (s->chip->flags & SCCNXP_HAVE_IO)
977 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
978 }
979
980 /* Disable interrupts */
981 s->imr = 0;
982 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
983
984 if (!s->poll) {
985 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
986 sccnxp_ist,
987 IRQF_TRIGGER_FALLING |
988 IRQF_ONESHOT,
989 dev_name(&pdev->dev), s);
990 if (!ret)
991 return 0;
992
993 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
994 } else {
995 init_timer(&s->timer);
996 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s);
997 mod_timer(&s->timer, jiffies +
998 usecs_to_jiffies(s->pdata.poll_time_us));
999 return 0;
1000 }
1001
1002 uart_unregister_driver(&s->uart);
1003 err_out:
1004 if (!IS_ERR(s->regulator))
1005 return regulator_disable(s->regulator);
1006
1007 return ret;
1008 }
1009
1010 static int sccnxp_remove(struct platform_device *pdev)
1011 {
1012 int i;
1013 struct sccnxp_port *s = platform_get_drvdata(pdev);
1014
1015 if (!s->poll)
1016 devm_free_irq(&pdev->dev, s->irq, s);
1017 else
1018 del_timer_sync(&s->timer);
1019
1020 for (i = 0; i < s->uart.nr; i++)
1021 uart_remove_one_port(&s->uart, &s->port[i]);
1022
1023 uart_unregister_driver(&s->uart);
1024
1025 if (!IS_ERR(s->regulator))
1026 return regulator_disable(s->regulator);
1027
1028 return 0;
1029 }
1030
1031 static struct platform_driver sccnxp_uart_driver = {
1032 .driver = {
1033 .name = SCCNXP_NAME,
1034 },
1035 .probe = sccnxp_probe,
1036 .remove = sccnxp_remove,
1037 .id_table = sccnxp_id_table,
1038 };
1039 module_platform_driver(sccnxp_uart_driver);
1040
1041 MODULE_LICENSE("GPL v2");
1042 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1043 MODULE_DESCRIPTION("SCCNXP serial driver");
1044
1045
1046
1047
1048
1049 /* LDV_COMMENT_BEGIN_MAIN */
1050 #ifdef LDV_MAIN0_sequence_infinite_withcheck_stateful
1051
1052 /*###########################################################################*/
1053
1054 /*############## Driver Environment Generator 0.2 output ####################*/
1055
1056 /*###########################################################################*/
1057
1058
1059
1060 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test if all kernel resources are correctly released by driver before driver will be unloaded. */
1061 void ldv_check_final_state(void);
1062
1063 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result. */
1064 void ldv_check_return_value(int res);
1065
1066 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result of probe() function. */
1067 void ldv_check_return_value_probe(int res);
1068
1069 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Initializes the model. */
1070 void ldv_initialize(void);
1071
1072 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Reinitializes the model between distinct model function calls. */
1073 void ldv_handler_precall(void);
1074
1075 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Returns arbitrary interger value. */
1076 int nondet_int(void);
1077
1078 /* LDV_COMMENT_VAR_DECLARE_LDV Special variable for LDV verifier. */
1079 int LDV_IN_INTERRUPT;
1080
1081 /* LDV_COMMENT_FUNCTION_MAIN Main function for LDV verifier. */
1082 void ldv_main0_sequence_infinite_withcheck_stateful(void) {
1083
1084
1085
1086 /* LDV_COMMENT_BEGIN_VARIABLE_DECLARATION_PART */
1087 /*============================= VARIABLE DECLARATION PART =============================*/
1088 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
1089 /* content: static unsigned int sccnxp_tx_empty(struct uart_port *port)*/
1090 /* LDV_COMMENT_BEGIN_PREP */
1091 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1092 #define SUPPORT_SYSRQ
1093 #endif
1094 #define SCCNXP_NAME "uart-sccnxp"
1095 #define SCCNXP_MAJOR 204
1096 #define SCCNXP_MINOR 205
1097 #define SCCNXP_MR_REG (0x00)
1098 # define MR0_BAUD_NORMAL (0 << 0)
1099 # define MR0_BAUD_EXT1 (1 << 0)
1100 # define MR0_BAUD_EXT2 (5 << 0)
1101 # define MR0_FIFO (1 << 3)
1102 # define MR0_TXLVL (1 << 4)
1103 # define MR1_BITS_5 (0 << 0)
1104 # define MR1_BITS_6 (1 << 0)
1105 # define MR1_BITS_7 (2 << 0)
1106 # define MR1_BITS_8 (3 << 0)
1107 # define MR1_PAR_EVN (0 << 2)
1108 # define MR1_PAR_ODD (1 << 2)
1109 # define MR1_PAR_NO (4 << 2)
1110 # define MR2_STOP1 (7 << 0)
1111 # define MR2_STOP2 (0xf << 0)
1112 #define SCCNXP_SR_REG (0x01)
1113 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1114 # define SR_RXRDY (1 << 0)
1115 # define SR_FULL (1 << 1)
1116 # define SR_TXRDY (1 << 2)
1117 # define SR_TXEMT (1 << 3)
1118 # define SR_OVR (1 << 4)
1119 # define SR_PE (1 << 5)
1120 # define SR_FE (1 << 6)
1121 # define SR_BRK (1 << 7)
1122 #define SCCNXP_CR_REG (0x02)
1123 # define CR_RX_ENABLE (1 << 0)
1124 # define CR_RX_DISABLE (1 << 1)
1125 # define CR_TX_ENABLE (1 << 2)
1126 # define CR_TX_DISABLE (1 << 3)
1127 # define CR_CMD_MRPTR1 (0x01 << 4)
1128 # define CR_CMD_RX_RESET (0x02 << 4)
1129 # define CR_CMD_TX_RESET (0x03 << 4)
1130 # define CR_CMD_STATUS_RESET (0x04 << 4)
1131 # define CR_CMD_BREAK_RESET (0x05 << 4)
1132 # define CR_CMD_START_BREAK (0x06 << 4)
1133 # define CR_CMD_STOP_BREAK (0x07 << 4)
1134 # define CR_CMD_MRPTR0 (0x0b << 4)
1135 #define SCCNXP_RHR_REG (0x03)
1136 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1137 #define SCCNXP_IPCR_REG (0x04)
1138 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1139 # define ACR_BAUD0 (0 << 7)
1140 # define ACR_BAUD1 (1 << 7)
1141 # define ACR_TIMER_MODE (6 << 4)
1142 #define SCCNXP_ISR_REG (0x05)
1143 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1144 # define IMR_TXRDY (1 << 0)
1145 # define IMR_RXRDY (1 << 1)
1146 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1147 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1148 #define SCCNXP_IPR_REG (0x0d)
1149 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1150 #define SCCNXP_SOP_REG (0x0e)
1151 #define SCCNXP_ROP_REG (0x0f)
1152 #define MCTRL_MASK(sig) (0xf << (sig))
1153 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1154 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1155 #define SCCNXP_HAVE_IO 0x00000001
1156 #define SCCNXP_HAVE_MR0 0x00000002
1157 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1158 #endif
1159 /* LDV_COMMENT_END_PREP */
1160 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_tx_empty" */
1161 struct uart_port * var_group1;
1162 /* LDV_COMMENT_BEGIN_PREP */
1163 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1164 #endif
1165 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1166 #endif
1167 /* LDV_COMMENT_END_PREP */
1168 /* content: static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)*/
1169 /* LDV_COMMENT_BEGIN_PREP */
1170 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1171 #define SUPPORT_SYSRQ
1172 #endif
1173 #define SCCNXP_NAME "uart-sccnxp"
1174 #define SCCNXP_MAJOR 204
1175 #define SCCNXP_MINOR 205
1176 #define SCCNXP_MR_REG (0x00)
1177 # define MR0_BAUD_NORMAL (0 << 0)
1178 # define MR0_BAUD_EXT1 (1 << 0)
1179 # define MR0_BAUD_EXT2 (5 << 0)
1180 # define MR0_FIFO (1 << 3)
1181 # define MR0_TXLVL (1 << 4)
1182 # define MR1_BITS_5 (0 << 0)
1183 # define MR1_BITS_6 (1 << 0)
1184 # define MR1_BITS_7 (2 << 0)
1185 # define MR1_BITS_8 (3 << 0)
1186 # define MR1_PAR_EVN (0 << 2)
1187 # define MR1_PAR_ODD (1 << 2)
1188 # define MR1_PAR_NO (4 << 2)
1189 # define MR2_STOP1 (7 << 0)
1190 # define MR2_STOP2 (0xf << 0)
1191 #define SCCNXP_SR_REG (0x01)
1192 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1193 # define SR_RXRDY (1 << 0)
1194 # define SR_FULL (1 << 1)
1195 # define SR_TXRDY (1 << 2)
1196 # define SR_TXEMT (1 << 3)
1197 # define SR_OVR (1 << 4)
1198 # define SR_PE (1 << 5)
1199 # define SR_FE (1 << 6)
1200 # define SR_BRK (1 << 7)
1201 #define SCCNXP_CR_REG (0x02)
1202 # define CR_RX_ENABLE (1 << 0)
1203 # define CR_RX_DISABLE (1 << 1)
1204 # define CR_TX_ENABLE (1 << 2)
1205 # define CR_TX_DISABLE (1 << 3)
1206 # define CR_CMD_MRPTR1 (0x01 << 4)
1207 # define CR_CMD_RX_RESET (0x02 << 4)
1208 # define CR_CMD_TX_RESET (0x03 << 4)
1209 # define CR_CMD_STATUS_RESET (0x04 << 4)
1210 # define CR_CMD_BREAK_RESET (0x05 << 4)
1211 # define CR_CMD_START_BREAK (0x06 << 4)
1212 # define CR_CMD_STOP_BREAK (0x07 << 4)
1213 # define CR_CMD_MRPTR0 (0x0b << 4)
1214 #define SCCNXP_RHR_REG (0x03)
1215 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1216 #define SCCNXP_IPCR_REG (0x04)
1217 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1218 # define ACR_BAUD0 (0 << 7)
1219 # define ACR_BAUD1 (1 << 7)
1220 # define ACR_TIMER_MODE (6 << 4)
1221 #define SCCNXP_ISR_REG (0x05)
1222 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1223 # define IMR_TXRDY (1 << 0)
1224 # define IMR_RXRDY (1 << 1)
1225 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1226 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1227 #define SCCNXP_IPR_REG (0x0d)
1228 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1229 #define SCCNXP_SOP_REG (0x0e)
1230 #define SCCNXP_ROP_REG (0x0f)
1231 #define MCTRL_MASK(sig) (0xf << (sig))
1232 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1233 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1234 #define SCCNXP_HAVE_IO 0x00000001
1235 #define SCCNXP_HAVE_MR0 0x00000002
1236 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1237 #endif
1238 /* LDV_COMMENT_END_PREP */
1239 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_mctrl" */
1240 unsigned int var_sccnxp_set_mctrl_18_p1;
1241 /* LDV_COMMENT_BEGIN_PREP */
1242 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1243 #endif
1244 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1245 #endif
1246 /* LDV_COMMENT_END_PREP */
1247 /* content: static unsigned int sccnxp_get_mctrl(struct uart_port *port)*/
1248 /* LDV_COMMENT_BEGIN_PREP */
1249 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1250 #define SUPPORT_SYSRQ
1251 #endif
1252 #define SCCNXP_NAME "uart-sccnxp"
1253 #define SCCNXP_MAJOR 204
1254 #define SCCNXP_MINOR 205
1255 #define SCCNXP_MR_REG (0x00)
1256 # define MR0_BAUD_NORMAL (0 << 0)
1257 # define MR0_BAUD_EXT1 (1 << 0)
1258 # define MR0_BAUD_EXT2 (5 << 0)
1259 # define MR0_FIFO (1 << 3)
1260 # define MR0_TXLVL (1 << 4)
1261 # define MR1_BITS_5 (0 << 0)
1262 # define MR1_BITS_6 (1 << 0)
1263 # define MR1_BITS_7 (2 << 0)
1264 # define MR1_BITS_8 (3 << 0)
1265 # define MR1_PAR_EVN (0 << 2)
1266 # define MR1_PAR_ODD (1 << 2)
1267 # define MR1_PAR_NO (4 << 2)
1268 # define MR2_STOP1 (7 << 0)
1269 # define MR2_STOP2 (0xf << 0)
1270 #define SCCNXP_SR_REG (0x01)
1271 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1272 # define SR_RXRDY (1 << 0)
1273 # define SR_FULL (1 << 1)
1274 # define SR_TXRDY (1 << 2)
1275 # define SR_TXEMT (1 << 3)
1276 # define SR_OVR (1 << 4)
1277 # define SR_PE (1 << 5)
1278 # define SR_FE (1 << 6)
1279 # define SR_BRK (1 << 7)
1280 #define SCCNXP_CR_REG (0x02)
1281 # define CR_RX_ENABLE (1 << 0)
1282 # define CR_RX_DISABLE (1 << 1)
1283 # define CR_TX_ENABLE (1 << 2)
1284 # define CR_TX_DISABLE (1 << 3)
1285 # define CR_CMD_MRPTR1 (0x01 << 4)
1286 # define CR_CMD_RX_RESET (0x02 << 4)
1287 # define CR_CMD_TX_RESET (0x03 << 4)
1288 # define CR_CMD_STATUS_RESET (0x04 << 4)
1289 # define CR_CMD_BREAK_RESET (0x05 << 4)
1290 # define CR_CMD_START_BREAK (0x06 << 4)
1291 # define CR_CMD_STOP_BREAK (0x07 << 4)
1292 # define CR_CMD_MRPTR0 (0x0b << 4)
1293 #define SCCNXP_RHR_REG (0x03)
1294 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1295 #define SCCNXP_IPCR_REG (0x04)
1296 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1297 # define ACR_BAUD0 (0 << 7)
1298 # define ACR_BAUD1 (1 << 7)
1299 # define ACR_TIMER_MODE (6 << 4)
1300 #define SCCNXP_ISR_REG (0x05)
1301 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1302 # define IMR_TXRDY (1 << 0)
1303 # define IMR_RXRDY (1 << 1)
1304 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1305 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1306 #define SCCNXP_IPR_REG (0x0d)
1307 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1308 #define SCCNXP_SOP_REG (0x0e)
1309 #define SCCNXP_ROP_REG (0x0f)
1310 #define MCTRL_MASK(sig) (0xf << (sig))
1311 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1312 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1313 #define SCCNXP_HAVE_IO 0x00000001
1314 #define SCCNXP_HAVE_MR0 0x00000002
1315 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1316 #endif
1317 /* LDV_COMMENT_END_PREP */
1318 /* LDV_COMMENT_BEGIN_PREP */
1319 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1320 #endif
1321 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1322 #endif
1323 /* LDV_COMMENT_END_PREP */
1324 /* content: static void sccnxp_stop_tx(struct uart_port *port)*/
1325 /* LDV_COMMENT_BEGIN_PREP */
1326 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1327 #define SUPPORT_SYSRQ
1328 #endif
1329 #define SCCNXP_NAME "uart-sccnxp"
1330 #define SCCNXP_MAJOR 204
1331 #define SCCNXP_MINOR 205
1332 #define SCCNXP_MR_REG (0x00)
1333 # define MR0_BAUD_NORMAL (0 << 0)
1334 # define MR0_BAUD_EXT1 (1 << 0)
1335 # define MR0_BAUD_EXT2 (5 << 0)
1336 # define MR0_FIFO (1 << 3)
1337 # define MR0_TXLVL (1 << 4)
1338 # define MR1_BITS_5 (0 << 0)
1339 # define MR1_BITS_6 (1 << 0)
1340 # define MR1_BITS_7 (2 << 0)
1341 # define MR1_BITS_8 (3 << 0)
1342 # define MR1_PAR_EVN (0 << 2)
1343 # define MR1_PAR_ODD (1 << 2)
1344 # define MR1_PAR_NO (4 << 2)
1345 # define MR2_STOP1 (7 << 0)
1346 # define MR2_STOP2 (0xf << 0)
1347 #define SCCNXP_SR_REG (0x01)
1348 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1349 # define SR_RXRDY (1 << 0)
1350 # define SR_FULL (1 << 1)
1351 # define SR_TXRDY (1 << 2)
1352 # define SR_TXEMT (1 << 3)
1353 # define SR_OVR (1 << 4)
1354 # define SR_PE (1 << 5)
1355 # define SR_FE (1 << 6)
1356 # define SR_BRK (1 << 7)
1357 #define SCCNXP_CR_REG (0x02)
1358 # define CR_RX_ENABLE (1 << 0)
1359 # define CR_RX_DISABLE (1 << 1)
1360 # define CR_TX_ENABLE (1 << 2)
1361 # define CR_TX_DISABLE (1 << 3)
1362 # define CR_CMD_MRPTR1 (0x01 << 4)
1363 # define CR_CMD_RX_RESET (0x02 << 4)
1364 # define CR_CMD_TX_RESET (0x03 << 4)
1365 # define CR_CMD_STATUS_RESET (0x04 << 4)
1366 # define CR_CMD_BREAK_RESET (0x05 << 4)
1367 # define CR_CMD_START_BREAK (0x06 << 4)
1368 # define CR_CMD_STOP_BREAK (0x07 << 4)
1369 # define CR_CMD_MRPTR0 (0x0b << 4)
1370 #define SCCNXP_RHR_REG (0x03)
1371 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1372 #define SCCNXP_IPCR_REG (0x04)
1373 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1374 # define ACR_BAUD0 (0 << 7)
1375 # define ACR_BAUD1 (1 << 7)
1376 # define ACR_TIMER_MODE (6 << 4)
1377 #define SCCNXP_ISR_REG (0x05)
1378 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1379 # define IMR_TXRDY (1 << 0)
1380 # define IMR_RXRDY (1 << 1)
1381 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1382 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1383 #define SCCNXP_IPR_REG (0x0d)
1384 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1385 #define SCCNXP_SOP_REG (0x0e)
1386 #define SCCNXP_ROP_REG (0x0f)
1387 #define MCTRL_MASK(sig) (0xf << (sig))
1388 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1389 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1390 #define SCCNXP_HAVE_IO 0x00000001
1391 #define SCCNXP_HAVE_MR0 0x00000002
1392 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1393 #endif
1394 /* LDV_COMMENT_END_PREP */
1395 /* LDV_COMMENT_BEGIN_PREP */
1396 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1397 #endif
1398 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1399 #endif
1400 /* LDV_COMMENT_END_PREP */
1401 /* content: static void sccnxp_start_tx(struct uart_port *port)*/
1402 /* LDV_COMMENT_BEGIN_PREP */
1403 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1404 #define SUPPORT_SYSRQ
1405 #endif
1406 #define SCCNXP_NAME "uart-sccnxp"
1407 #define SCCNXP_MAJOR 204
1408 #define SCCNXP_MINOR 205
1409 #define SCCNXP_MR_REG (0x00)
1410 # define MR0_BAUD_NORMAL (0 << 0)
1411 # define MR0_BAUD_EXT1 (1 << 0)
1412 # define MR0_BAUD_EXT2 (5 << 0)
1413 # define MR0_FIFO (1 << 3)
1414 # define MR0_TXLVL (1 << 4)
1415 # define MR1_BITS_5 (0 << 0)
1416 # define MR1_BITS_6 (1 << 0)
1417 # define MR1_BITS_7 (2 << 0)
1418 # define MR1_BITS_8 (3 << 0)
1419 # define MR1_PAR_EVN (0 << 2)
1420 # define MR1_PAR_ODD (1 << 2)
1421 # define MR1_PAR_NO (4 << 2)
1422 # define MR2_STOP1 (7 << 0)
1423 # define MR2_STOP2 (0xf << 0)
1424 #define SCCNXP_SR_REG (0x01)
1425 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1426 # define SR_RXRDY (1 << 0)
1427 # define SR_FULL (1 << 1)
1428 # define SR_TXRDY (1 << 2)
1429 # define SR_TXEMT (1 << 3)
1430 # define SR_OVR (1 << 4)
1431 # define SR_PE (1 << 5)
1432 # define SR_FE (1 << 6)
1433 # define SR_BRK (1 << 7)
1434 #define SCCNXP_CR_REG (0x02)
1435 # define CR_RX_ENABLE (1 << 0)
1436 # define CR_RX_DISABLE (1 << 1)
1437 # define CR_TX_ENABLE (1 << 2)
1438 # define CR_TX_DISABLE (1 << 3)
1439 # define CR_CMD_MRPTR1 (0x01 << 4)
1440 # define CR_CMD_RX_RESET (0x02 << 4)
1441 # define CR_CMD_TX_RESET (0x03 << 4)
1442 # define CR_CMD_STATUS_RESET (0x04 << 4)
1443 # define CR_CMD_BREAK_RESET (0x05 << 4)
1444 # define CR_CMD_START_BREAK (0x06 << 4)
1445 # define CR_CMD_STOP_BREAK (0x07 << 4)
1446 # define CR_CMD_MRPTR0 (0x0b << 4)
1447 #define SCCNXP_RHR_REG (0x03)
1448 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1449 #define SCCNXP_IPCR_REG (0x04)
1450 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1451 # define ACR_BAUD0 (0 << 7)
1452 # define ACR_BAUD1 (1 << 7)
1453 # define ACR_TIMER_MODE (6 << 4)
1454 #define SCCNXP_ISR_REG (0x05)
1455 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1456 # define IMR_TXRDY (1 << 0)
1457 # define IMR_RXRDY (1 << 1)
1458 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1459 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1460 #define SCCNXP_IPR_REG (0x0d)
1461 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1462 #define SCCNXP_SOP_REG (0x0e)
1463 #define SCCNXP_ROP_REG (0x0f)
1464 #define MCTRL_MASK(sig) (0xf << (sig))
1465 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1466 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1467 #define SCCNXP_HAVE_IO 0x00000001
1468 #define SCCNXP_HAVE_MR0 0x00000002
1469 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1470 #endif
1471 /* LDV_COMMENT_END_PREP */
1472 /* LDV_COMMENT_BEGIN_PREP */
1473 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1474 #endif
1475 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1476 #endif
1477 /* LDV_COMMENT_END_PREP */
1478 /* content: static void sccnxp_stop_rx(struct uart_port *port)*/
1479 /* LDV_COMMENT_BEGIN_PREP */
1480 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1481 #define SUPPORT_SYSRQ
1482 #endif
1483 #define SCCNXP_NAME "uart-sccnxp"
1484 #define SCCNXP_MAJOR 204
1485 #define SCCNXP_MINOR 205
1486 #define SCCNXP_MR_REG (0x00)
1487 # define MR0_BAUD_NORMAL (0 << 0)
1488 # define MR0_BAUD_EXT1 (1 << 0)
1489 # define MR0_BAUD_EXT2 (5 << 0)
1490 # define MR0_FIFO (1 << 3)
1491 # define MR0_TXLVL (1 << 4)
1492 # define MR1_BITS_5 (0 << 0)
1493 # define MR1_BITS_6 (1 << 0)
1494 # define MR1_BITS_7 (2 << 0)
1495 # define MR1_BITS_8 (3 << 0)
1496 # define MR1_PAR_EVN (0 << 2)
1497 # define MR1_PAR_ODD (1 << 2)
1498 # define MR1_PAR_NO (4 << 2)
1499 # define MR2_STOP1 (7 << 0)
1500 # define MR2_STOP2 (0xf << 0)
1501 #define SCCNXP_SR_REG (0x01)
1502 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1503 # define SR_RXRDY (1 << 0)
1504 # define SR_FULL (1 << 1)
1505 # define SR_TXRDY (1 << 2)
1506 # define SR_TXEMT (1 << 3)
1507 # define SR_OVR (1 << 4)
1508 # define SR_PE (1 << 5)
1509 # define SR_FE (1 << 6)
1510 # define SR_BRK (1 << 7)
1511 #define SCCNXP_CR_REG (0x02)
1512 # define CR_RX_ENABLE (1 << 0)
1513 # define CR_RX_DISABLE (1 << 1)
1514 # define CR_TX_ENABLE (1 << 2)
1515 # define CR_TX_DISABLE (1 << 3)
1516 # define CR_CMD_MRPTR1 (0x01 << 4)
1517 # define CR_CMD_RX_RESET (0x02 << 4)
1518 # define CR_CMD_TX_RESET (0x03 << 4)
1519 # define CR_CMD_STATUS_RESET (0x04 << 4)
1520 # define CR_CMD_BREAK_RESET (0x05 << 4)
1521 # define CR_CMD_START_BREAK (0x06 << 4)
1522 # define CR_CMD_STOP_BREAK (0x07 << 4)
1523 # define CR_CMD_MRPTR0 (0x0b << 4)
1524 #define SCCNXP_RHR_REG (0x03)
1525 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1526 #define SCCNXP_IPCR_REG (0x04)
1527 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1528 # define ACR_BAUD0 (0 << 7)
1529 # define ACR_BAUD1 (1 << 7)
1530 # define ACR_TIMER_MODE (6 << 4)
1531 #define SCCNXP_ISR_REG (0x05)
1532 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1533 # define IMR_TXRDY (1 << 0)
1534 # define IMR_RXRDY (1 << 1)
1535 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1536 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1537 #define SCCNXP_IPR_REG (0x0d)
1538 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1539 #define SCCNXP_SOP_REG (0x0e)
1540 #define SCCNXP_ROP_REG (0x0f)
1541 #define MCTRL_MASK(sig) (0xf << (sig))
1542 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1543 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1544 #define SCCNXP_HAVE_IO 0x00000001
1545 #define SCCNXP_HAVE_MR0 0x00000002
1546 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1547 #endif
1548 /* LDV_COMMENT_END_PREP */
1549 /* LDV_COMMENT_BEGIN_PREP */
1550 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1551 #endif
1552 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1553 #endif
1554 /* LDV_COMMENT_END_PREP */
1555 /* content: static void sccnxp_break_ctl(struct uart_port *port, int break_state)*/
1556 /* LDV_COMMENT_BEGIN_PREP */
1557 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1558 #define SUPPORT_SYSRQ
1559 #endif
1560 #define SCCNXP_NAME "uart-sccnxp"
1561 #define SCCNXP_MAJOR 204
1562 #define SCCNXP_MINOR 205
1563 #define SCCNXP_MR_REG (0x00)
1564 # define MR0_BAUD_NORMAL (0 << 0)
1565 # define MR0_BAUD_EXT1 (1 << 0)
1566 # define MR0_BAUD_EXT2 (5 << 0)
1567 # define MR0_FIFO (1 << 3)
1568 # define MR0_TXLVL (1 << 4)
1569 # define MR1_BITS_5 (0 << 0)
1570 # define MR1_BITS_6 (1 << 0)
1571 # define MR1_BITS_7 (2 << 0)
1572 # define MR1_BITS_8 (3 << 0)
1573 # define MR1_PAR_EVN (0 << 2)
1574 # define MR1_PAR_ODD (1 << 2)
1575 # define MR1_PAR_NO (4 << 2)
1576 # define MR2_STOP1 (7 << 0)
1577 # define MR2_STOP2 (0xf << 0)
1578 #define SCCNXP_SR_REG (0x01)
1579 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1580 # define SR_RXRDY (1 << 0)
1581 # define SR_FULL (1 << 1)
1582 # define SR_TXRDY (1 << 2)
1583 # define SR_TXEMT (1 << 3)
1584 # define SR_OVR (1 << 4)
1585 # define SR_PE (1 << 5)
1586 # define SR_FE (1 << 6)
1587 # define SR_BRK (1 << 7)
1588 #define SCCNXP_CR_REG (0x02)
1589 # define CR_RX_ENABLE (1 << 0)
1590 # define CR_RX_DISABLE (1 << 1)
1591 # define CR_TX_ENABLE (1 << 2)
1592 # define CR_TX_DISABLE (1 << 3)
1593 # define CR_CMD_MRPTR1 (0x01 << 4)
1594 # define CR_CMD_RX_RESET (0x02 << 4)
1595 # define CR_CMD_TX_RESET (0x03 << 4)
1596 # define CR_CMD_STATUS_RESET (0x04 << 4)
1597 # define CR_CMD_BREAK_RESET (0x05 << 4)
1598 # define CR_CMD_START_BREAK (0x06 << 4)
1599 # define CR_CMD_STOP_BREAK (0x07 << 4)
1600 # define CR_CMD_MRPTR0 (0x0b << 4)
1601 #define SCCNXP_RHR_REG (0x03)
1602 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1603 #define SCCNXP_IPCR_REG (0x04)
1604 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1605 # define ACR_BAUD0 (0 << 7)
1606 # define ACR_BAUD1 (1 << 7)
1607 # define ACR_TIMER_MODE (6 << 4)
1608 #define SCCNXP_ISR_REG (0x05)
1609 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1610 # define IMR_TXRDY (1 << 0)
1611 # define IMR_RXRDY (1 << 1)
1612 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1613 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1614 #define SCCNXP_IPR_REG (0x0d)
1615 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1616 #define SCCNXP_SOP_REG (0x0e)
1617 #define SCCNXP_ROP_REG (0x0f)
1618 #define MCTRL_MASK(sig) (0xf << (sig))
1619 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1620 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1621 #define SCCNXP_HAVE_IO 0x00000001
1622 #define SCCNXP_HAVE_MR0 0x00000002
1623 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1624 #endif
1625 /* LDV_COMMENT_END_PREP */
1626 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_break_ctl" */
1627 int var_sccnxp_break_ctl_20_p1;
1628 /* LDV_COMMENT_BEGIN_PREP */
1629 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1630 #endif
1631 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1632 #endif
1633 /* LDV_COMMENT_END_PREP */
1634 /* content: static int sccnxp_startup(struct uart_port *port)*/
1635 /* LDV_COMMENT_BEGIN_PREP */
1636 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1637 #define SUPPORT_SYSRQ
1638 #endif
1639 #define SCCNXP_NAME "uart-sccnxp"
1640 #define SCCNXP_MAJOR 204
1641 #define SCCNXP_MINOR 205
1642 #define SCCNXP_MR_REG (0x00)
1643 # define MR0_BAUD_NORMAL (0 << 0)
1644 # define MR0_BAUD_EXT1 (1 << 0)
1645 # define MR0_BAUD_EXT2 (5 << 0)
1646 # define MR0_FIFO (1 << 3)
1647 # define MR0_TXLVL (1 << 4)
1648 # define MR1_BITS_5 (0 << 0)
1649 # define MR1_BITS_6 (1 << 0)
1650 # define MR1_BITS_7 (2 << 0)
1651 # define MR1_BITS_8 (3 << 0)
1652 # define MR1_PAR_EVN (0 << 2)
1653 # define MR1_PAR_ODD (1 << 2)
1654 # define MR1_PAR_NO (4 << 2)
1655 # define MR2_STOP1 (7 << 0)
1656 # define MR2_STOP2 (0xf << 0)
1657 #define SCCNXP_SR_REG (0x01)
1658 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1659 # define SR_RXRDY (1 << 0)
1660 # define SR_FULL (1 << 1)
1661 # define SR_TXRDY (1 << 2)
1662 # define SR_TXEMT (1 << 3)
1663 # define SR_OVR (1 << 4)
1664 # define SR_PE (1 << 5)
1665 # define SR_FE (1 << 6)
1666 # define SR_BRK (1 << 7)
1667 #define SCCNXP_CR_REG (0x02)
1668 # define CR_RX_ENABLE (1 << 0)
1669 # define CR_RX_DISABLE (1 << 1)
1670 # define CR_TX_ENABLE (1 << 2)
1671 # define CR_TX_DISABLE (1 << 3)
1672 # define CR_CMD_MRPTR1 (0x01 << 4)
1673 # define CR_CMD_RX_RESET (0x02 << 4)
1674 # define CR_CMD_TX_RESET (0x03 << 4)
1675 # define CR_CMD_STATUS_RESET (0x04 << 4)
1676 # define CR_CMD_BREAK_RESET (0x05 << 4)
1677 # define CR_CMD_START_BREAK (0x06 << 4)
1678 # define CR_CMD_STOP_BREAK (0x07 << 4)
1679 # define CR_CMD_MRPTR0 (0x0b << 4)
1680 #define SCCNXP_RHR_REG (0x03)
1681 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1682 #define SCCNXP_IPCR_REG (0x04)
1683 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1684 # define ACR_BAUD0 (0 << 7)
1685 # define ACR_BAUD1 (1 << 7)
1686 # define ACR_TIMER_MODE (6 << 4)
1687 #define SCCNXP_ISR_REG (0x05)
1688 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1689 # define IMR_TXRDY (1 << 0)
1690 # define IMR_RXRDY (1 << 1)
1691 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1692 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1693 #define SCCNXP_IPR_REG (0x0d)
1694 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1695 #define SCCNXP_SOP_REG (0x0e)
1696 #define SCCNXP_ROP_REG (0x0f)
1697 #define MCTRL_MASK(sig) (0xf << (sig))
1698 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1699 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1700 #define SCCNXP_HAVE_IO 0x00000001
1701 #define SCCNXP_HAVE_MR0 0x00000002
1702 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1703 #endif
1704 /* LDV_COMMENT_END_PREP */
1705 /* LDV_COMMENT_BEGIN_PREP */
1706 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1707 #endif
1708 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1709 #endif
1710 /* LDV_COMMENT_END_PREP */
1711 /* content: static void sccnxp_shutdown(struct uart_port *port)*/
1712 /* LDV_COMMENT_BEGIN_PREP */
1713 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1714 #define SUPPORT_SYSRQ
1715 #endif
1716 #define SCCNXP_NAME "uart-sccnxp"
1717 #define SCCNXP_MAJOR 204
1718 #define SCCNXP_MINOR 205
1719 #define SCCNXP_MR_REG (0x00)
1720 # define MR0_BAUD_NORMAL (0 << 0)
1721 # define MR0_BAUD_EXT1 (1 << 0)
1722 # define MR0_BAUD_EXT2 (5 << 0)
1723 # define MR0_FIFO (1 << 3)
1724 # define MR0_TXLVL (1 << 4)
1725 # define MR1_BITS_5 (0 << 0)
1726 # define MR1_BITS_6 (1 << 0)
1727 # define MR1_BITS_7 (2 << 0)
1728 # define MR1_BITS_8 (3 << 0)
1729 # define MR1_PAR_EVN (0 << 2)
1730 # define MR1_PAR_ODD (1 << 2)
1731 # define MR1_PAR_NO (4 << 2)
1732 # define MR2_STOP1 (7 << 0)
1733 # define MR2_STOP2 (0xf << 0)
1734 #define SCCNXP_SR_REG (0x01)
1735 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1736 # define SR_RXRDY (1 << 0)
1737 # define SR_FULL (1 << 1)
1738 # define SR_TXRDY (1 << 2)
1739 # define SR_TXEMT (1 << 3)
1740 # define SR_OVR (1 << 4)
1741 # define SR_PE (1 << 5)
1742 # define SR_FE (1 << 6)
1743 # define SR_BRK (1 << 7)
1744 #define SCCNXP_CR_REG (0x02)
1745 # define CR_RX_ENABLE (1 << 0)
1746 # define CR_RX_DISABLE (1 << 1)
1747 # define CR_TX_ENABLE (1 << 2)
1748 # define CR_TX_DISABLE (1 << 3)
1749 # define CR_CMD_MRPTR1 (0x01 << 4)
1750 # define CR_CMD_RX_RESET (0x02 << 4)
1751 # define CR_CMD_TX_RESET (0x03 << 4)
1752 # define CR_CMD_STATUS_RESET (0x04 << 4)
1753 # define CR_CMD_BREAK_RESET (0x05 << 4)
1754 # define CR_CMD_START_BREAK (0x06 << 4)
1755 # define CR_CMD_STOP_BREAK (0x07 << 4)
1756 # define CR_CMD_MRPTR0 (0x0b << 4)
1757 #define SCCNXP_RHR_REG (0x03)
1758 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1759 #define SCCNXP_IPCR_REG (0x04)
1760 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1761 # define ACR_BAUD0 (0 << 7)
1762 # define ACR_BAUD1 (1 << 7)
1763 # define ACR_TIMER_MODE (6 << 4)
1764 #define SCCNXP_ISR_REG (0x05)
1765 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1766 # define IMR_TXRDY (1 << 0)
1767 # define IMR_RXRDY (1 << 1)
1768 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1769 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1770 #define SCCNXP_IPR_REG (0x0d)
1771 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1772 #define SCCNXP_SOP_REG (0x0e)
1773 #define SCCNXP_ROP_REG (0x0f)
1774 #define MCTRL_MASK(sig) (0xf << (sig))
1775 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1776 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1777 #define SCCNXP_HAVE_IO 0x00000001
1778 #define SCCNXP_HAVE_MR0 0x00000002
1779 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1780 #endif
1781 /* LDV_COMMENT_END_PREP */
1782 /* LDV_COMMENT_BEGIN_PREP */
1783 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1784 #endif
1785 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1786 #endif
1787 /* LDV_COMMENT_END_PREP */
1788 /* content: static void sccnxp_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)*/
1789 /* LDV_COMMENT_BEGIN_PREP */
1790 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1791 #define SUPPORT_SYSRQ
1792 #endif
1793 #define SCCNXP_NAME "uart-sccnxp"
1794 #define SCCNXP_MAJOR 204
1795 #define SCCNXP_MINOR 205
1796 #define SCCNXP_MR_REG (0x00)
1797 # define MR0_BAUD_NORMAL (0 << 0)
1798 # define MR0_BAUD_EXT1 (1 << 0)
1799 # define MR0_BAUD_EXT2 (5 << 0)
1800 # define MR0_FIFO (1 << 3)
1801 # define MR0_TXLVL (1 << 4)
1802 # define MR1_BITS_5 (0 << 0)
1803 # define MR1_BITS_6 (1 << 0)
1804 # define MR1_BITS_7 (2 << 0)
1805 # define MR1_BITS_8 (3 << 0)
1806 # define MR1_PAR_EVN (0 << 2)
1807 # define MR1_PAR_ODD (1 << 2)
1808 # define MR1_PAR_NO (4 << 2)
1809 # define MR2_STOP1 (7 << 0)
1810 # define MR2_STOP2 (0xf << 0)
1811 #define SCCNXP_SR_REG (0x01)
1812 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1813 # define SR_RXRDY (1 << 0)
1814 # define SR_FULL (1 << 1)
1815 # define SR_TXRDY (1 << 2)
1816 # define SR_TXEMT (1 << 3)
1817 # define SR_OVR (1 << 4)
1818 # define SR_PE (1 << 5)
1819 # define SR_FE (1 << 6)
1820 # define SR_BRK (1 << 7)
1821 #define SCCNXP_CR_REG (0x02)
1822 # define CR_RX_ENABLE (1 << 0)
1823 # define CR_RX_DISABLE (1 << 1)
1824 # define CR_TX_ENABLE (1 << 2)
1825 # define CR_TX_DISABLE (1 << 3)
1826 # define CR_CMD_MRPTR1 (0x01 << 4)
1827 # define CR_CMD_RX_RESET (0x02 << 4)
1828 # define CR_CMD_TX_RESET (0x03 << 4)
1829 # define CR_CMD_STATUS_RESET (0x04 << 4)
1830 # define CR_CMD_BREAK_RESET (0x05 << 4)
1831 # define CR_CMD_START_BREAK (0x06 << 4)
1832 # define CR_CMD_STOP_BREAK (0x07 << 4)
1833 # define CR_CMD_MRPTR0 (0x0b << 4)
1834 #define SCCNXP_RHR_REG (0x03)
1835 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1836 #define SCCNXP_IPCR_REG (0x04)
1837 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1838 # define ACR_BAUD0 (0 << 7)
1839 # define ACR_BAUD1 (1 << 7)
1840 # define ACR_TIMER_MODE (6 << 4)
1841 #define SCCNXP_ISR_REG (0x05)
1842 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1843 # define IMR_TXRDY (1 << 0)
1844 # define IMR_RXRDY (1 << 1)
1845 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1846 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1847 #define SCCNXP_IPR_REG (0x0d)
1848 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1849 #define SCCNXP_SOP_REG (0x0e)
1850 #define SCCNXP_ROP_REG (0x0f)
1851 #define MCTRL_MASK(sig) (0xf << (sig))
1852 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1853 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1854 #define SCCNXP_HAVE_IO 0x00000001
1855 #define SCCNXP_HAVE_MR0 0x00000002
1856 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1857 #endif
1858 /* LDV_COMMENT_END_PREP */
1859 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_termios" */
1860 struct ktermios * var_group2;
1861 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_termios" */
1862 struct ktermios * var_sccnxp_set_termios_21_p2;
1863 /* LDV_COMMENT_BEGIN_PREP */
1864 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1865 #endif
1866 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1867 #endif
1868 /* LDV_COMMENT_END_PREP */
1869 /* content: static const char *sccnxp_type(struct uart_port *port)*/
1870 /* LDV_COMMENT_BEGIN_PREP */
1871 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1872 #define SUPPORT_SYSRQ
1873 #endif
1874 #define SCCNXP_NAME "uart-sccnxp"
1875 #define SCCNXP_MAJOR 204
1876 #define SCCNXP_MINOR 205
1877 #define SCCNXP_MR_REG (0x00)
1878 # define MR0_BAUD_NORMAL (0 << 0)
1879 # define MR0_BAUD_EXT1 (1 << 0)
1880 # define MR0_BAUD_EXT2 (5 << 0)
1881 # define MR0_FIFO (1 << 3)
1882 # define MR0_TXLVL (1 << 4)
1883 # define MR1_BITS_5 (0 << 0)
1884 # define MR1_BITS_6 (1 << 0)
1885 # define MR1_BITS_7 (2 << 0)
1886 # define MR1_BITS_8 (3 << 0)
1887 # define MR1_PAR_EVN (0 << 2)
1888 # define MR1_PAR_ODD (1 << 2)
1889 # define MR1_PAR_NO (4 << 2)
1890 # define MR2_STOP1 (7 << 0)
1891 # define MR2_STOP2 (0xf << 0)
1892 #define SCCNXP_SR_REG (0x01)
1893 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1894 # define SR_RXRDY (1 << 0)
1895 # define SR_FULL (1 << 1)
1896 # define SR_TXRDY (1 << 2)
1897 # define SR_TXEMT (1 << 3)
1898 # define SR_OVR (1 << 4)
1899 # define SR_PE (1 << 5)
1900 # define SR_FE (1 << 6)
1901 # define SR_BRK (1 << 7)
1902 #define SCCNXP_CR_REG (0x02)
1903 # define CR_RX_ENABLE (1 << 0)
1904 # define CR_RX_DISABLE (1 << 1)
1905 # define CR_TX_ENABLE (1 << 2)
1906 # define CR_TX_DISABLE (1 << 3)
1907 # define CR_CMD_MRPTR1 (0x01 << 4)
1908 # define CR_CMD_RX_RESET (0x02 << 4)
1909 # define CR_CMD_TX_RESET (0x03 << 4)
1910 # define CR_CMD_STATUS_RESET (0x04 << 4)
1911 # define CR_CMD_BREAK_RESET (0x05 << 4)
1912 # define CR_CMD_START_BREAK (0x06 << 4)
1913 # define CR_CMD_STOP_BREAK (0x07 << 4)
1914 # define CR_CMD_MRPTR0 (0x0b << 4)
1915 #define SCCNXP_RHR_REG (0x03)
1916 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1917 #define SCCNXP_IPCR_REG (0x04)
1918 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1919 # define ACR_BAUD0 (0 << 7)
1920 # define ACR_BAUD1 (1 << 7)
1921 # define ACR_TIMER_MODE (6 << 4)
1922 #define SCCNXP_ISR_REG (0x05)
1923 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
1924 # define IMR_TXRDY (1 << 0)
1925 # define IMR_RXRDY (1 << 1)
1926 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
1927 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
1928 #define SCCNXP_IPR_REG (0x0d)
1929 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
1930 #define SCCNXP_SOP_REG (0x0e)
1931 #define SCCNXP_ROP_REG (0x0f)
1932 #define MCTRL_MASK(sig) (0xf << (sig))
1933 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
1934 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
1935 #define SCCNXP_HAVE_IO 0x00000001
1936 #define SCCNXP_HAVE_MR0 0x00000002
1937 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1938 #endif
1939 /* LDV_COMMENT_END_PREP */
1940 /* LDV_COMMENT_BEGIN_PREP */
1941 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1942 #endif
1943 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
1944 #endif
1945 /* LDV_COMMENT_END_PREP */
1946 /* content: static void sccnxp_release_port(struct uart_port *port)*/
1947 /* LDV_COMMENT_BEGIN_PREP */
1948 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1949 #define SUPPORT_SYSRQ
1950 #endif
1951 #define SCCNXP_NAME "uart-sccnxp"
1952 #define SCCNXP_MAJOR 204
1953 #define SCCNXP_MINOR 205
1954 #define SCCNXP_MR_REG (0x00)
1955 # define MR0_BAUD_NORMAL (0 << 0)
1956 # define MR0_BAUD_EXT1 (1 << 0)
1957 # define MR0_BAUD_EXT2 (5 << 0)
1958 # define MR0_FIFO (1 << 3)
1959 # define MR0_TXLVL (1 << 4)
1960 # define MR1_BITS_5 (0 << 0)
1961 # define MR1_BITS_6 (1 << 0)
1962 # define MR1_BITS_7 (2 << 0)
1963 # define MR1_BITS_8 (3 << 0)
1964 # define MR1_PAR_EVN (0 << 2)
1965 # define MR1_PAR_ODD (1 << 2)
1966 # define MR1_PAR_NO (4 << 2)
1967 # define MR2_STOP1 (7 << 0)
1968 # define MR2_STOP2 (0xf << 0)
1969 #define SCCNXP_SR_REG (0x01)
1970 #define SCCNXP_CSR_REG SCCNXP_SR_REG
1971 # define SR_RXRDY (1 << 0)
1972 # define SR_FULL (1 << 1)
1973 # define SR_TXRDY (1 << 2)
1974 # define SR_TXEMT (1 << 3)
1975 # define SR_OVR (1 << 4)
1976 # define SR_PE (1 << 5)
1977 # define SR_FE (1 << 6)
1978 # define SR_BRK (1 << 7)
1979 #define SCCNXP_CR_REG (0x02)
1980 # define CR_RX_ENABLE (1 << 0)
1981 # define CR_RX_DISABLE (1 << 1)
1982 # define CR_TX_ENABLE (1 << 2)
1983 # define CR_TX_DISABLE (1 << 3)
1984 # define CR_CMD_MRPTR1 (0x01 << 4)
1985 # define CR_CMD_RX_RESET (0x02 << 4)
1986 # define CR_CMD_TX_RESET (0x03 << 4)
1987 # define CR_CMD_STATUS_RESET (0x04 << 4)
1988 # define CR_CMD_BREAK_RESET (0x05 << 4)
1989 # define CR_CMD_START_BREAK (0x06 << 4)
1990 # define CR_CMD_STOP_BREAK (0x07 << 4)
1991 # define CR_CMD_MRPTR0 (0x0b << 4)
1992 #define SCCNXP_RHR_REG (0x03)
1993 #define SCCNXP_THR_REG SCCNXP_RHR_REG
1994 #define SCCNXP_IPCR_REG (0x04)
1995 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
1996 # define ACR_BAUD0 (0 << 7)
1997 # define ACR_BAUD1 (1 << 7)
1998 # define ACR_TIMER_MODE (6 << 4)
1999 #define SCCNXP_ISR_REG (0x05)
2000 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2001 # define IMR_TXRDY (1 << 0)
2002 # define IMR_RXRDY (1 << 1)
2003 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2004 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2005 #define SCCNXP_IPR_REG (0x0d)
2006 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2007 #define SCCNXP_SOP_REG (0x0e)
2008 #define SCCNXP_ROP_REG (0x0f)
2009 #define MCTRL_MASK(sig) (0xf << (sig))
2010 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2011 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2012 #define SCCNXP_HAVE_IO 0x00000001
2013 #define SCCNXP_HAVE_MR0 0x00000002
2014 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2015 #endif
2016 /* LDV_COMMENT_END_PREP */
2017 /* LDV_COMMENT_BEGIN_PREP */
2018 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2019 #endif
2020 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2021 #endif
2022 /* LDV_COMMENT_END_PREP */
2023 /* content: static int sccnxp_request_port(struct uart_port *port)*/
2024 /* LDV_COMMENT_BEGIN_PREP */
2025 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2026 #define SUPPORT_SYSRQ
2027 #endif
2028 #define SCCNXP_NAME "uart-sccnxp"
2029 #define SCCNXP_MAJOR 204
2030 #define SCCNXP_MINOR 205
2031 #define SCCNXP_MR_REG (0x00)
2032 # define MR0_BAUD_NORMAL (0 << 0)
2033 # define MR0_BAUD_EXT1 (1 << 0)
2034 # define MR0_BAUD_EXT2 (5 << 0)
2035 # define MR0_FIFO (1 << 3)
2036 # define MR0_TXLVL (1 << 4)
2037 # define MR1_BITS_5 (0 << 0)
2038 # define MR1_BITS_6 (1 << 0)
2039 # define MR1_BITS_7 (2 << 0)
2040 # define MR1_BITS_8 (3 << 0)
2041 # define MR1_PAR_EVN (0 << 2)
2042 # define MR1_PAR_ODD (1 << 2)
2043 # define MR1_PAR_NO (4 << 2)
2044 # define MR2_STOP1 (7 << 0)
2045 # define MR2_STOP2 (0xf << 0)
2046 #define SCCNXP_SR_REG (0x01)
2047 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2048 # define SR_RXRDY (1 << 0)
2049 # define SR_FULL (1 << 1)
2050 # define SR_TXRDY (1 << 2)
2051 # define SR_TXEMT (1 << 3)
2052 # define SR_OVR (1 << 4)
2053 # define SR_PE (1 << 5)
2054 # define SR_FE (1 << 6)
2055 # define SR_BRK (1 << 7)
2056 #define SCCNXP_CR_REG (0x02)
2057 # define CR_RX_ENABLE (1 << 0)
2058 # define CR_RX_DISABLE (1 << 1)
2059 # define CR_TX_ENABLE (1 << 2)
2060 # define CR_TX_DISABLE (1 << 3)
2061 # define CR_CMD_MRPTR1 (0x01 << 4)
2062 # define CR_CMD_RX_RESET (0x02 << 4)
2063 # define CR_CMD_TX_RESET (0x03 << 4)
2064 # define CR_CMD_STATUS_RESET (0x04 << 4)
2065 # define CR_CMD_BREAK_RESET (0x05 << 4)
2066 # define CR_CMD_START_BREAK (0x06 << 4)
2067 # define CR_CMD_STOP_BREAK (0x07 << 4)
2068 # define CR_CMD_MRPTR0 (0x0b << 4)
2069 #define SCCNXP_RHR_REG (0x03)
2070 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2071 #define SCCNXP_IPCR_REG (0x04)
2072 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2073 # define ACR_BAUD0 (0 << 7)
2074 # define ACR_BAUD1 (1 << 7)
2075 # define ACR_TIMER_MODE (6 << 4)
2076 #define SCCNXP_ISR_REG (0x05)
2077 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2078 # define IMR_TXRDY (1 << 0)
2079 # define IMR_RXRDY (1 << 1)
2080 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2081 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2082 #define SCCNXP_IPR_REG (0x0d)
2083 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2084 #define SCCNXP_SOP_REG (0x0e)
2085 #define SCCNXP_ROP_REG (0x0f)
2086 #define MCTRL_MASK(sig) (0xf << (sig))
2087 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2088 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2089 #define SCCNXP_HAVE_IO 0x00000001
2090 #define SCCNXP_HAVE_MR0 0x00000002
2091 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2092 #endif
2093 /* LDV_COMMENT_END_PREP */
2094 /* LDV_COMMENT_BEGIN_PREP */
2095 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2096 #endif
2097 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2098 #endif
2099 /* LDV_COMMENT_END_PREP */
2100 /* content: static void sccnxp_config_port(struct uart_port *port, int flags)*/
2101 /* LDV_COMMENT_BEGIN_PREP */
2102 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2103 #define SUPPORT_SYSRQ
2104 #endif
2105 #define SCCNXP_NAME "uart-sccnxp"
2106 #define SCCNXP_MAJOR 204
2107 #define SCCNXP_MINOR 205
2108 #define SCCNXP_MR_REG (0x00)
2109 # define MR0_BAUD_NORMAL (0 << 0)
2110 # define MR0_BAUD_EXT1 (1 << 0)
2111 # define MR0_BAUD_EXT2 (5 << 0)
2112 # define MR0_FIFO (1 << 3)
2113 # define MR0_TXLVL (1 << 4)
2114 # define MR1_BITS_5 (0 << 0)
2115 # define MR1_BITS_6 (1 << 0)
2116 # define MR1_BITS_7 (2 << 0)
2117 # define MR1_BITS_8 (3 << 0)
2118 # define MR1_PAR_EVN (0 << 2)
2119 # define MR1_PAR_ODD (1 << 2)
2120 # define MR1_PAR_NO (4 << 2)
2121 # define MR2_STOP1 (7 << 0)
2122 # define MR2_STOP2 (0xf << 0)
2123 #define SCCNXP_SR_REG (0x01)
2124 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2125 # define SR_RXRDY (1 << 0)
2126 # define SR_FULL (1 << 1)
2127 # define SR_TXRDY (1 << 2)
2128 # define SR_TXEMT (1 << 3)
2129 # define SR_OVR (1 << 4)
2130 # define SR_PE (1 << 5)
2131 # define SR_FE (1 << 6)
2132 # define SR_BRK (1 << 7)
2133 #define SCCNXP_CR_REG (0x02)
2134 # define CR_RX_ENABLE (1 << 0)
2135 # define CR_RX_DISABLE (1 << 1)
2136 # define CR_TX_ENABLE (1 << 2)
2137 # define CR_TX_DISABLE (1 << 3)
2138 # define CR_CMD_MRPTR1 (0x01 << 4)
2139 # define CR_CMD_RX_RESET (0x02 << 4)
2140 # define CR_CMD_TX_RESET (0x03 << 4)
2141 # define CR_CMD_STATUS_RESET (0x04 << 4)
2142 # define CR_CMD_BREAK_RESET (0x05 << 4)
2143 # define CR_CMD_START_BREAK (0x06 << 4)
2144 # define CR_CMD_STOP_BREAK (0x07 << 4)
2145 # define CR_CMD_MRPTR0 (0x0b << 4)
2146 #define SCCNXP_RHR_REG (0x03)
2147 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2148 #define SCCNXP_IPCR_REG (0x04)
2149 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2150 # define ACR_BAUD0 (0 << 7)
2151 # define ACR_BAUD1 (1 << 7)
2152 # define ACR_TIMER_MODE (6 << 4)
2153 #define SCCNXP_ISR_REG (0x05)
2154 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2155 # define IMR_TXRDY (1 << 0)
2156 # define IMR_RXRDY (1 << 1)
2157 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2158 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2159 #define SCCNXP_IPR_REG (0x0d)
2160 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2161 #define SCCNXP_SOP_REG (0x0e)
2162 #define SCCNXP_ROP_REG (0x0f)
2163 #define MCTRL_MASK(sig) (0xf << (sig))
2164 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2165 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2166 #define SCCNXP_HAVE_IO 0x00000001
2167 #define SCCNXP_HAVE_MR0 0x00000002
2168 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2169 #endif
2170 /* LDV_COMMENT_END_PREP */
2171 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_config_port" */
2172 int var_sccnxp_config_port_27_p1;
2173 /* LDV_COMMENT_BEGIN_PREP */
2174 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2175 #endif
2176 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2177 #endif
2178 /* LDV_COMMENT_END_PREP */
2179 /* content: static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)*/
2180 /* LDV_COMMENT_BEGIN_PREP */
2181 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2182 #define SUPPORT_SYSRQ
2183 #endif
2184 #define SCCNXP_NAME "uart-sccnxp"
2185 #define SCCNXP_MAJOR 204
2186 #define SCCNXP_MINOR 205
2187 #define SCCNXP_MR_REG (0x00)
2188 # define MR0_BAUD_NORMAL (0 << 0)
2189 # define MR0_BAUD_EXT1 (1 << 0)
2190 # define MR0_BAUD_EXT2 (5 << 0)
2191 # define MR0_FIFO (1 << 3)
2192 # define MR0_TXLVL (1 << 4)
2193 # define MR1_BITS_5 (0 << 0)
2194 # define MR1_BITS_6 (1 << 0)
2195 # define MR1_BITS_7 (2 << 0)
2196 # define MR1_BITS_8 (3 << 0)
2197 # define MR1_PAR_EVN (0 << 2)
2198 # define MR1_PAR_ODD (1 << 2)
2199 # define MR1_PAR_NO (4 << 2)
2200 # define MR2_STOP1 (7 << 0)
2201 # define MR2_STOP2 (0xf << 0)
2202 #define SCCNXP_SR_REG (0x01)
2203 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2204 # define SR_RXRDY (1 << 0)
2205 # define SR_FULL (1 << 1)
2206 # define SR_TXRDY (1 << 2)
2207 # define SR_TXEMT (1 << 3)
2208 # define SR_OVR (1 << 4)
2209 # define SR_PE (1 << 5)
2210 # define SR_FE (1 << 6)
2211 # define SR_BRK (1 << 7)
2212 #define SCCNXP_CR_REG (0x02)
2213 # define CR_RX_ENABLE (1 << 0)
2214 # define CR_RX_DISABLE (1 << 1)
2215 # define CR_TX_ENABLE (1 << 2)
2216 # define CR_TX_DISABLE (1 << 3)
2217 # define CR_CMD_MRPTR1 (0x01 << 4)
2218 # define CR_CMD_RX_RESET (0x02 << 4)
2219 # define CR_CMD_TX_RESET (0x03 << 4)
2220 # define CR_CMD_STATUS_RESET (0x04 << 4)
2221 # define CR_CMD_BREAK_RESET (0x05 << 4)
2222 # define CR_CMD_START_BREAK (0x06 << 4)
2223 # define CR_CMD_STOP_BREAK (0x07 << 4)
2224 # define CR_CMD_MRPTR0 (0x0b << 4)
2225 #define SCCNXP_RHR_REG (0x03)
2226 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2227 #define SCCNXP_IPCR_REG (0x04)
2228 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2229 # define ACR_BAUD0 (0 << 7)
2230 # define ACR_BAUD1 (1 << 7)
2231 # define ACR_TIMER_MODE (6 << 4)
2232 #define SCCNXP_ISR_REG (0x05)
2233 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2234 # define IMR_TXRDY (1 << 0)
2235 # define IMR_RXRDY (1 << 1)
2236 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2237 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2238 #define SCCNXP_IPR_REG (0x0d)
2239 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2240 #define SCCNXP_SOP_REG (0x0e)
2241 #define SCCNXP_ROP_REG (0x0f)
2242 #define MCTRL_MASK(sig) (0xf << (sig))
2243 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2244 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2245 #define SCCNXP_HAVE_IO 0x00000001
2246 #define SCCNXP_HAVE_MR0 0x00000002
2247 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2248 #endif
2249 /* LDV_COMMENT_END_PREP */
2250 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_verify_port" */
2251 struct serial_struct * var_group3;
2252 /* LDV_COMMENT_BEGIN_PREP */
2253 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2254 #endif
2255 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2256 #endif
2257 /* LDV_COMMENT_END_PREP */
2258
2259 /** STRUCT: struct type: platform_driver, struct name: sccnxp_uart_driver **/
2260 /* content: static int sccnxp_probe(struct platform_device *pdev)*/
2261 /* LDV_COMMENT_BEGIN_PREP */
2262 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2263 #define SUPPORT_SYSRQ
2264 #endif
2265 #define SCCNXP_NAME "uart-sccnxp"
2266 #define SCCNXP_MAJOR 204
2267 #define SCCNXP_MINOR 205
2268 #define SCCNXP_MR_REG (0x00)
2269 # define MR0_BAUD_NORMAL (0 << 0)
2270 # define MR0_BAUD_EXT1 (1 << 0)
2271 # define MR0_BAUD_EXT2 (5 << 0)
2272 # define MR0_FIFO (1 << 3)
2273 # define MR0_TXLVL (1 << 4)
2274 # define MR1_BITS_5 (0 << 0)
2275 # define MR1_BITS_6 (1 << 0)
2276 # define MR1_BITS_7 (2 << 0)
2277 # define MR1_BITS_8 (3 << 0)
2278 # define MR1_PAR_EVN (0 << 2)
2279 # define MR1_PAR_ODD (1 << 2)
2280 # define MR1_PAR_NO (4 << 2)
2281 # define MR2_STOP1 (7 << 0)
2282 # define MR2_STOP2 (0xf << 0)
2283 #define SCCNXP_SR_REG (0x01)
2284 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2285 # define SR_RXRDY (1 << 0)
2286 # define SR_FULL (1 << 1)
2287 # define SR_TXRDY (1 << 2)
2288 # define SR_TXEMT (1 << 3)
2289 # define SR_OVR (1 << 4)
2290 # define SR_PE (1 << 5)
2291 # define SR_FE (1 << 6)
2292 # define SR_BRK (1 << 7)
2293 #define SCCNXP_CR_REG (0x02)
2294 # define CR_RX_ENABLE (1 << 0)
2295 # define CR_RX_DISABLE (1 << 1)
2296 # define CR_TX_ENABLE (1 << 2)
2297 # define CR_TX_DISABLE (1 << 3)
2298 # define CR_CMD_MRPTR1 (0x01 << 4)
2299 # define CR_CMD_RX_RESET (0x02 << 4)
2300 # define CR_CMD_TX_RESET (0x03 << 4)
2301 # define CR_CMD_STATUS_RESET (0x04 << 4)
2302 # define CR_CMD_BREAK_RESET (0x05 << 4)
2303 # define CR_CMD_START_BREAK (0x06 << 4)
2304 # define CR_CMD_STOP_BREAK (0x07 << 4)
2305 # define CR_CMD_MRPTR0 (0x0b << 4)
2306 #define SCCNXP_RHR_REG (0x03)
2307 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2308 #define SCCNXP_IPCR_REG (0x04)
2309 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2310 # define ACR_BAUD0 (0 << 7)
2311 # define ACR_BAUD1 (1 << 7)
2312 # define ACR_TIMER_MODE (6 << 4)
2313 #define SCCNXP_ISR_REG (0x05)
2314 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2315 # define IMR_TXRDY (1 << 0)
2316 # define IMR_RXRDY (1 << 1)
2317 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2318 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2319 #define SCCNXP_IPR_REG (0x0d)
2320 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2321 #define SCCNXP_SOP_REG (0x0e)
2322 #define SCCNXP_ROP_REG (0x0f)
2323 #define MCTRL_MASK(sig) (0xf << (sig))
2324 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2325 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2326 #define SCCNXP_HAVE_IO 0x00000001
2327 #define SCCNXP_HAVE_MR0 0x00000002
2328 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2329 #endif
2330 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2331 #endif
2332 /* LDV_COMMENT_END_PREP */
2333 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_probe" */
2334 struct platform_device * var_group4;
2335 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "sccnxp_probe" */
2336 static int res_sccnxp_probe_32;
2337 /* content: static int sccnxp_remove(struct platform_device *pdev)*/
2338 /* LDV_COMMENT_BEGIN_PREP */
2339 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2340 #define SUPPORT_SYSRQ
2341 #endif
2342 #define SCCNXP_NAME "uart-sccnxp"
2343 #define SCCNXP_MAJOR 204
2344 #define SCCNXP_MINOR 205
2345 #define SCCNXP_MR_REG (0x00)
2346 # define MR0_BAUD_NORMAL (0 << 0)
2347 # define MR0_BAUD_EXT1 (1 << 0)
2348 # define MR0_BAUD_EXT2 (5 << 0)
2349 # define MR0_FIFO (1 << 3)
2350 # define MR0_TXLVL (1 << 4)
2351 # define MR1_BITS_5 (0 << 0)
2352 # define MR1_BITS_6 (1 << 0)
2353 # define MR1_BITS_7 (2 << 0)
2354 # define MR1_BITS_8 (3 << 0)
2355 # define MR1_PAR_EVN (0 << 2)
2356 # define MR1_PAR_ODD (1 << 2)
2357 # define MR1_PAR_NO (4 << 2)
2358 # define MR2_STOP1 (7 << 0)
2359 # define MR2_STOP2 (0xf << 0)
2360 #define SCCNXP_SR_REG (0x01)
2361 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2362 # define SR_RXRDY (1 << 0)
2363 # define SR_FULL (1 << 1)
2364 # define SR_TXRDY (1 << 2)
2365 # define SR_TXEMT (1 << 3)
2366 # define SR_OVR (1 << 4)
2367 # define SR_PE (1 << 5)
2368 # define SR_FE (1 << 6)
2369 # define SR_BRK (1 << 7)
2370 #define SCCNXP_CR_REG (0x02)
2371 # define CR_RX_ENABLE (1 << 0)
2372 # define CR_RX_DISABLE (1 << 1)
2373 # define CR_TX_ENABLE (1 << 2)
2374 # define CR_TX_DISABLE (1 << 3)
2375 # define CR_CMD_MRPTR1 (0x01 << 4)
2376 # define CR_CMD_RX_RESET (0x02 << 4)
2377 # define CR_CMD_TX_RESET (0x03 << 4)
2378 # define CR_CMD_STATUS_RESET (0x04 << 4)
2379 # define CR_CMD_BREAK_RESET (0x05 << 4)
2380 # define CR_CMD_START_BREAK (0x06 << 4)
2381 # define CR_CMD_STOP_BREAK (0x07 << 4)
2382 # define CR_CMD_MRPTR0 (0x0b << 4)
2383 #define SCCNXP_RHR_REG (0x03)
2384 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2385 #define SCCNXP_IPCR_REG (0x04)
2386 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2387 # define ACR_BAUD0 (0 << 7)
2388 # define ACR_BAUD1 (1 << 7)
2389 # define ACR_TIMER_MODE (6 << 4)
2390 #define SCCNXP_ISR_REG (0x05)
2391 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2392 # define IMR_TXRDY (1 << 0)
2393 # define IMR_RXRDY (1 << 1)
2394 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2395 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2396 #define SCCNXP_IPR_REG (0x0d)
2397 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2398 #define SCCNXP_SOP_REG (0x0e)
2399 #define SCCNXP_ROP_REG (0x0f)
2400 #define MCTRL_MASK(sig) (0xf << (sig))
2401 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2402 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2403 #define SCCNXP_HAVE_IO 0x00000001
2404 #define SCCNXP_HAVE_MR0 0x00000002
2405 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2406 #endif
2407 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2408 #endif
2409 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2410 #endif
2411 /* LDV_COMMENT_END_PREP */
2412
2413 /** CALLBACK SECTION request_irq **/
2414 /* content: static irqreturn_t sccnxp_ist(int irq, void *dev_id)*/
2415 /* LDV_COMMENT_BEGIN_PREP */
2416 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2417 #define SUPPORT_SYSRQ
2418 #endif
2419 #define SCCNXP_NAME "uart-sccnxp"
2420 #define SCCNXP_MAJOR 204
2421 #define SCCNXP_MINOR 205
2422 #define SCCNXP_MR_REG (0x00)
2423 # define MR0_BAUD_NORMAL (0 << 0)
2424 # define MR0_BAUD_EXT1 (1 << 0)
2425 # define MR0_BAUD_EXT2 (5 << 0)
2426 # define MR0_FIFO (1 << 3)
2427 # define MR0_TXLVL (1 << 4)
2428 # define MR1_BITS_5 (0 << 0)
2429 # define MR1_BITS_6 (1 << 0)
2430 # define MR1_BITS_7 (2 << 0)
2431 # define MR1_BITS_8 (3 << 0)
2432 # define MR1_PAR_EVN (0 << 2)
2433 # define MR1_PAR_ODD (1 << 2)
2434 # define MR1_PAR_NO (4 << 2)
2435 # define MR2_STOP1 (7 << 0)
2436 # define MR2_STOP2 (0xf << 0)
2437 #define SCCNXP_SR_REG (0x01)
2438 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2439 # define SR_RXRDY (1 << 0)
2440 # define SR_FULL (1 << 1)
2441 # define SR_TXRDY (1 << 2)
2442 # define SR_TXEMT (1 << 3)
2443 # define SR_OVR (1 << 4)
2444 # define SR_PE (1 << 5)
2445 # define SR_FE (1 << 6)
2446 # define SR_BRK (1 << 7)
2447 #define SCCNXP_CR_REG (0x02)
2448 # define CR_RX_ENABLE (1 << 0)
2449 # define CR_RX_DISABLE (1 << 1)
2450 # define CR_TX_ENABLE (1 << 2)
2451 # define CR_TX_DISABLE (1 << 3)
2452 # define CR_CMD_MRPTR1 (0x01 << 4)
2453 # define CR_CMD_RX_RESET (0x02 << 4)
2454 # define CR_CMD_TX_RESET (0x03 << 4)
2455 # define CR_CMD_STATUS_RESET (0x04 << 4)
2456 # define CR_CMD_BREAK_RESET (0x05 << 4)
2457 # define CR_CMD_START_BREAK (0x06 << 4)
2458 # define CR_CMD_STOP_BREAK (0x07 << 4)
2459 # define CR_CMD_MRPTR0 (0x0b << 4)
2460 #define SCCNXP_RHR_REG (0x03)
2461 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2462 #define SCCNXP_IPCR_REG (0x04)
2463 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2464 # define ACR_BAUD0 (0 << 7)
2465 # define ACR_BAUD1 (1 << 7)
2466 # define ACR_TIMER_MODE (6 << 4)
2467 #define SCCNXP_ISR_REG (0x05)
2468 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2469 # define IMR_TXRDY (1 << 0)
2470 # define IMR_RXRDY (1 << 1)
2471 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2472 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2473 #define SCCNXP_IPR_REG (0x0d)
2474 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2475 #define SCCNXP_SOP_REG (0x0e)
2476 #define SCCNXP_ROP_REG (0x0f)
2477 #define MCTRL_MASK(sig) (0xf << (sig))
2478 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2479 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2480 #define SCCNXP_HAVE_IO 0x00000001
2481 #define SCCNXP_HAVE_MR0 0x00000002
2482 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2483 #endif
2484 /* LDV_COMMENT_END_PREP */
2485 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_ist" */
2486 int var_sccnxp_ist_13_p0;
2487 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_ist" */
2488 void * var_sccnxp_ist_13_p1;
2489 /* LDV_COMMENT_BEGIN_PREP */
2490 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2491 #endif
2492 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2493 #endif
2494 /* LDV_COMMENT_END_PREP */
2495
2496
2497
2498
2499 /* LDV_COMMENT_END_VARIABLE_DECLARATION_PART */
2500 /* LDV_COMMENT_BEGIN_VARIABLE_INITIALIZING_PART */
2501 /*============================= VARIABLE INITIALIZING PART =============================*/
2502 LDV_IN_INTERRUPT=1;
2503
2504
2505
2506
2507 /* LDV_COMMENT_END_VARIABLE_INITIALIZING_PART */
2508 /* LDV_COMMENT_BEGIN_FUNCTION_CALL_SECTION */
2509 /*============================= FUNCTION CALL SECTION =============================*/
2510 /* LDV_COMMENT_FUNCTION_CALL Initialize LDV model. */
2511 ldv_initialize();
2512
2513
2514 int ldv_s_sccnxp_uart_driver_platform_driver = 0;
2515
2516
2517
2518
2519 while( nondet_int()
2520 || !(ldv_s_sccnxp_uart_driver_platform_driver == 0)
2521 ) {
2522
2523 switch(nondet_int()) {
2524
2525 case 0: {
2526
2527 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2528
2529
2530 /* content: static unsigned int sccnxp_tx_empty(struct uart_port *port)*/
2531 /* LDV_COMMENT_BEGIN_PREP */
2532 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2533 #define SUPPORT_SYSRQ
2534 #endif
2535 #define SCCNXP_NAME "uart-sccnxp"
2536 #define SCCNXP_MAJOR 204
2537 #define SCCNXP_MINOR 205
2538 #define SCCNXP_MR_REG (0x00)
2539 # define MR0_BAUD_NORMAL (0 << 0)
2540 # define MR0_BAUD_EXT1 (1 << 0)
2541 # define MR0_BAUD_EXT2 (5 << 0)
2542 # define MR0_FIFO (1 << 3)
2543 # define MR0_TXLVL (1 << 4)
2544 # define MR1_BITS_5 (0 << 0)
2545 # define MR1_BITS_6 (1 << 0)
2546 # define MR1_BITS_7 (2 << 0)
2547 # define MR1_BITS_8 (3 << 0)
2548 # define MR1_PAR_EVN (0 << 2)
2549 # define MR1_PAR_ODD (1 << 2)
2550 # define MR1_PAR_NO (4 << 2)
2551 # define MR2_STOP1 (7 << 0)
2552 # define MR2_STOP2 (0xf << 0)
2553 #define SCCNXP_SR_REG (0x01)
2554 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2555 # define SR_RXRDY (1 << 0)
2556 # define SR_FULL (1 << 1)
2557 # define SR_TXRDY (1 << 2)
2558 # define SR_TXEMT (1 << 3)
2559 # define SR_OVR (1 << 4)
2560 # define SR_PE (1 << 5)
2561 # define SR_FE (1 << 6)
2562 # define SR_BRK (1 << 7)
2563 #define SCCNXP_CR_REG (0x02)
2564 # define CR_RX_ENABLE (1 << 0)
2565 # define CR_RX_DISABLE (1 << 1)
2566 # define CR_TX_ENABLE (1 << 2)
2567 # define CR_TX_DISABLE (1 << 3)
2568 # define CR_CMD_MRPTR1 (0x01 << 4)
2569 # define CR_CMD_RX_RESET (0x02 << 4)
2570 # define CR_CMD_TX_RESET (0x03 << 4)
2571 # define CR_CMD_STATUS_RESET (0x04 << 4)
2572 # define CR_CMD_BREAK_RESET (0x05 << 4)
2573 # define CR_CMD_START_BREAK (0x06 << 4)
2574 # define CR_CMD_STOP_BREAK (0x07 << 4)
2575 # define CR_CMD_MRPTR0 (0x0b << 4)
2576 #define SCCNXP_RHR_REG (0x03)
2577 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2578 #define SCCNXP_IPCR_REG (0x04)
2579 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2580 # define ACR_BAUD0 (0 << 7)
2581 # define ACR_BAUD1 (1 << 7)
2582 # define ACR_TIMER_MODE (6 << 4)
2583 #define SCCNXP_ISR_REG (0x05)
2584 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2585 # define IMR_TXRDY (1 << 0)
2586 # define IMR_RXRDY (1 << 1)
2587 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2588 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2589 #define SCCNXP_IPR_REG (0x0d)
2590 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2591 #define SCCNXP_SOP_REG (0x0e)
2592 #define SCCNXP_ROP_REG (0x0f)
2593 #define MCTRL_MASK(sig) (0xf << (sig))
2594 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2595 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2596 #define SCCNXP_HAVE_IO 0x00000001
2597 #define SCCNXP_HAVE_MR0 0x00000002
2598 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2599 #endif
2600 /* LDV_COMMENT_END_PREP */
2601 /* LDV_COMMENT_FUNCTION_CALL Function from field "tx_empty" from driver structure with callbacks "sccnxp_ops" */
2602 ldv_handler_precall();
2603 sccnxp_tx_empty( var_group1);
2604 /* LDV_COMMENT_BEGIN_PREP */
2605 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2606 #endif
2607 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2608 #endif
2609 /* LDV_COMMENT_END_PREP */
2610
2611
2612
2613
2614 }
2615
2616 break;
2617 case 1: {
2618
2619 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2620
2621
2622 /* content: static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)*/
2623 /* LDV_COMMENT_BEGIN_PREP */
2624 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2625 #define SUPPORT_SYSRQ
2626 #endif
2627 #define SCCNXP_NAME "uart-sccnxp"
2628 #define SCCNXP_MAJOR 204
2629 #define SCCNXP_MINOR 205
2630 #define SCCNXP_MR_REG (0x00)
2631 # define MR0_BAUD_NORMAL (0 << 0)
2632 # define MR0_BAUD_EXT1 (1 << 0)
2633 # define MR0_BAUD_EXT2 (5 << 0)
2634 # define MR0_FIFO (1 << 3)
2635 # define MR0_TXLVL (1 << 4)
2636 # define MR1_BITS_5 (0 << 0)
2637 # define MR1_BITS_6 (1 << 0)
2638 # define MR1_BITS_7 (2 << 0)
2639 # define MR1_BITS_8 (3 << 0)
2640 # define MR1_PAR_EVN (0 << 2)
2641 # define MR1_PAR_ODD (1 << 2)
2642 # define MR1_PAR_NO (4 << 2)
2643 # define MR2_STOP1 (7 << 0)
2644 # define MR2_STOP2 (0xf << 0)
2645 #define SCCNXP_SR_REG (0x01)
2646 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2647 # define SR_RXRDY (1 << 0)
2648 # define SR_FULL (1 << 1)
2649 # define SR_TXRDY (1 << 2)
2650 # define SR_TXEMT (1 << 3)
2651 # define SR_OVR (1 << 4)
2652 # define SR_PE (1 << 5)
2653 # define SR_FE (1 << 6)
2654 # define SR_BRK (1 << 7)
2655 #define SCCNXP_CR_REG (0x02)
2656 # define CR_RX_ENABLE (1 << 0)
2657 # define CR_RX_DISABLE (1 << 1)
2658 # define CR_TX_ENABLE (1 << 2)
2659 # define CR_TX_DISABLE (1 << 3)
2660 # define CR_CMD_MRPTR1 (0x01 << 4)
2661 # define CR_CMD_RX_RESET (0x02 << 4)
2662 # define CR_CMD_TX_RESET (0x03 << 4)
2663 # define CR_CMD_STATUS_RESET (0x04 << 4)
2664 # define CR_CMD_BREAK_RESET (0x05 << 4)
2665 # define CR_CMD_START_BREAK (0x06 << 4)
2666 # define CR_CMD_STOP_BREAK (0x07 << 4)
2667 # define CR_CMD_MRPTR0 (0x0b << 4)
2668 #define SCCNXP_RHR_REG (0x03)
2669 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2670 #define SCCNXP_IPCR_REG (0x04)
2671 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2672 # define ACR_BAUD0 (0 << 7)
2673 # define ACR_BAUD1 (1 << 7)
2674 # define ACR_TIMER_MODE (6 << 4)
2675 #define SCCNXP_ISR_REG (0x05)
2676 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2677 # define IMR_TXRDY (1 << 0)
2678 # define IMR_RXRDY (1 << 1)
2679 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2680 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2681 #define SCCNXP_IPR_REG (0x0d)
2682 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2683 #define SCCNXP_SOP_REG (0x0e)
2684 #define SCCNXP_ROP_REG (0x0f)
2685 #define MCTRL_MASK(sig) (0xf << (sig))
2686 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2687 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2688 #define SCCNXP_HAVE_IO 0x00000001
2689 #define SCCNXP_HAVE_MR0 0x00000002
2690 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2691 #endif
2692 /* LDV_COMMENT_END_PREP */
2693 /* LDV_COMMENT_FUNCTION_CALL Function from field "set_mctrl" from driver structure with callbacks "sccnxp_ops" */
2694 ldv_handler_precall();
2695 sccnxp_set_mctrl( var_group1, var_sccnxp_set_mctrl_18_p1);
2696 /* LDV_COMMENT_BEGIN_PREP */
2697 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2698 #endif
2699 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2700 #endif
2701 /* LDV_COMMENT_END_PREP */
2702
2703
2704
2705
2706 }
2707
2708 break;
2709 case 2: {
2710
2711 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2712
2713
2714 /* content: static unsigned int sccnxp_get_mctrl(struct uart_port *port)*/
2715 /* LDV_COMMENT_BEGIN_PREP */
2716 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2717 #define SUPPORT_SYSRQ
2718 #endif
2719 #define SCCNXP_NAME "uart-sccnxp"
2720 #define SCCNXP_MAJOR 204
2721 #define SCCNXP_MINOR 205
2722 #define SCCNXP_MR_REG (0x00)
2723 # define MR0_BAUD_NORMAL (0 << 0)
2724 # define MR0_BAUD_EXT1 (1 << 0)
2725 # define MR0_BAUD_EXT2 (5 << 0)
2726 # define MR0_FIFO (1 << 3)
2727 # define MR0_TXLVL (1 << 4)
2728 # define MR1_BITS_5 (0 << 0)
2729 # define MR1_BITS_6 (1 << 0)
2730 # define MR1_BITS_7 (2 << 0)
2731 # define MR1_BITS_8 (3 << 0)
2732 # define MR1_PAR_EVN (0 << 2)
2733 # define MR1_PAR_ODD (1 << 2)
2734 # define MR1_PAR_NO (4 << 2)
2735 # define MR2_STOP1 (7 << 0)
2736 # define MR2_STOP2 (0xf << 0)
2737 #define SCCNXP_SR_REG (0x01)
2738 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2739 # define SR_RXRDY (1 << 0)
2740 # define SR_FULL (1 << 1)
2741 # define SR_TXRDY (1 << 2)
2742 # define SR_TXEMT (1 << 3)
2743 # define SR_OVR (1 << 4)
2744 # define SR_PE (1 << 5)
2745 # define SR_FE (1 << 6)
2746 # define SR_BRK (1 << 7)
2747 #define SCCNXP_CR_REG (0x02)
2748 # define CR_RX_ENABLE (1 << 0)
2749 # define CR_RX_DISABLE (1 << 1)
2750 # define CR_TX_ENABLE (1 << 2)
2751 # define CR_TX_DISABLE (1 << 3)
2752 # define CR_CMD_MRPTR1 (0x01 << 4)
2753 # define CR_CMD_RX_RESET (0x02 << 4)
2754 # define CR_CMD_TX_RESET (0x03 << 4)
2755 # define CR_CMD_STATUS_RESET (0x04 << 4)
2756 # define CR_CMD_BREAK_RESET (0x05 << 4)
2757 # define CR_CMD_START_BREAK (0x06 << 4)
2758 # define CR_CMD_STOP_BREAK (0x07 << 4)
2759 # define CR_CMD_MRPTR0 (0x0b << 4)
2760 #define SCCNXP_RHR_REG (0x03)
2761 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2762 #define SCCNXP_IPCR_REG (0x04)
2763 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2764 # define ACR_BAUD0 (0 << 7)
2765 # define ACR_BAUD1 (1 << 7)
2766 # define ACR_TIMER_MODE (6 << 4)
2767 #define SCCNXP_ISR_REG (0x05)
2768 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2769 # define IMR_TXRDY (1 << 0)
2770 # define IMR_RXRDY (1 << 1)
2771 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2772 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2773 #define SCCNXP_IPR_REG (0x0d)
2774 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2775 #define SCCNXP_SOP_REG (0x0e)
2776 #define SCCNXP_ROP_REG (0x0f)
2777 #define MCTRL_MASK(sig) (0xf << (sig))
2778 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2779 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2780 #define SCCNXP_HAVE_IO 0x00000001
2781 #define SCCNXP_HAVE_MR0 0x00000002
2782 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2783 #endif
2784 /* LDV_COMMENT_END_PREP */
2785 /* LDV_COMMENT_FUNCTION_CALL Function from field "get_mctrl" from driver structure with callbacks "sccnxp_ops" */
2786 ldv_handler_precall();
2787 sccnxp_get_mctrl( var_group1);
2788 /* LDV_COMMENT_BEGIN_PREP */
2789 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2790 #endif
2791 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2792 #endif
2793 /* LDV_COMMENT_END_PREP */
2794
2795
2796
2797
2798 }
2799
2800 break;
2801 case 3: {
2802
2803 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2804
2805
2806 /* content: static void sccnxp_stop_tx(struct uart_port *port)*/
2807 /* LDV_COMMENT_BEGIN_PREP */
2808 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2809 #define SUPPORT_SYSRQ
2810 #endif
2811 #define SCCNXP_NAME "uart-sccnxp"
2812 #define SCCNXP_MAJOR 204
2813 #define SCCNXP_MINOR 205
2814 #define SCCNXP_MR_REG (0x00)
2815 # define MR0_BAUD_NORMAL (0 << 0)
2816 # define MR0_BAUD_EXT1 (1 << 0)
2817 # define MR0_BAUD_EXT2 (5 << 0)
2818 # define MR0_FIFO (1 << 3)
2819 # define MR0_TXLVL (1 << 4)
2820 # define MR1_BITS_5 (0 << 0)
2821 # define MR1_BITS_6 (1 << 0)
2822 # define MR1_BITS_7 (2 << 0)
2823 # define MR1_BITS_8 (3 << 0)
2824 # define MR1_PAR_EVN (0 << 2)
2825 # define MR1_PAR_ODD (1 << 2)
2826 # define MR1_PAR_NO (4 << 2)
2827 # define MR2_STOP1 (7 << 0)
2828 # define MR2_STOP2 (0xf << 0)
2829 #define SCCNXP_SR_REG (0x01)
2830 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2831 # define SR_RXRDY (1 << 0)
2832 # define SR_FULL (1 << 1)
2833 # define SR_TXRDY (1 << 2)
2834 # define SR_TXEMT (1 << 3)
2835 # define SR_OVR (1 << 4)
2836 # define SR_PE (1 << 5)
2837 # define SR_FE (1 << 6)
2838 # define SR_BRK (1 << 7)
2839 #define SCCNXP_CR_REG (0x02)
2840 # define CR_RX_ENABLE (1 << 0)
2841 # define CR_RX_DISABLE (1 << 1)
2842 # define CR_TX_ENABLE (1 << 2)
2843 # define CR_TX_DISABLE (1 << 3)
2844 # define CR_CMD_MRPTR1 (0x01 << 4)
2845 # define CR_CMD_RX_RESET (0x02 << 4)
2846 # define CR_CMD_TX_RESET (0x03 << 4)
2847 # define CR_CMD_STATUS_RESET (0x04 << 4)
2848 # define CR_CMD_BREAK_RESET (0x05 << 4)
2849 # define CR_CMD_START_BREAK (0x06 << 4)
2850 # define CR_CMD_STOP_BREAK (0x07 << 4)
2851 # define CR_CMD_MRPTR0 (0x0b << 4)
2852 #define SCCNXP_RHR_REG (0x03)
2853 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2854 #define SCCNXP_IPCR_REG (0x04)
2855 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2856 # define ACR_BAUD0 (0 << 7)
2857 # define ACR_BAUD1 (1 << 7)
2858 # define ACR_TIMER_MODE (6 << 4)
2859 #define SCCNXP_ISR_REG (0x05)
2860 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2861 # define IMR_TXRDY (1 << 0)
2862 # define IMR_RXRDY (1 << 1)
2863 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2864 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2865 #define SCCNXP_IPR_REG (0x0d)
2866 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2867 #define SCCNXP_SOP_REG (0x0e)
2868 #define SCCNXP_ROP_REG (0x0f)
2869 #define MCTRL_MASK(sig) (0xf << (sig))
2870 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2871 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2872 #define SCCNXP_HAVE_IO 0x00000001
2873 #define SCCNXP_HAVE_MR0 0x00000002
2874 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2875 #endif
2876 /* LDV_COMMENT_END_PREP */
2877 /* LDV_COMMENT_FUNCTION_CALL Function from field "stop_tx" from driver structure with callbacks "sccnxp_ops" */
2878 ldv_handler_precall();
2879 sccnxp_stop_tx( var_group1);
2880 /* LDV_COMMENT_BEGIN_PREP */
2881 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2882 #endif
2883 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2884 #endif
2885 /* LDV_COMMENT_END_PREP */
2886
2887
2888
2889
2890 }
2891
2892 break;
2893 case 4: {
2894
2895 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2896
2897
2898 /* content: static void sccnxp_start_tx(struct uart_port *port)*/
2899 /* LDV_COMMENT_BEGIN_PREP */
2900 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2901 #define SUPPORT_SYSRQ
2902 #endif
2903 #define SCCNXP_NAME "uart-sccnxp"
2904 #define SCCNXP_MAJOR 204
2905 #define SCCNXP_MINOR 205
2906 #define SCCNXP_MR_REG (0x00)
2907 # define MR0_BAUD_NORMAL (0 << 0)
2908 # define MR0_BAUD_EXT1 (1 << 0)
2909 # define MR0_BAUD_EXT2 (5 << 0)
2910 # define MR0_FIFO (1 << 3)
2911 # define MR0_TXLVL (1 << 4)
2912 # define MR1_BITS_5 (0 << 0)
2913 # define MR1_BITS_6 (1 << 0)
2914 # define MR1_BITS_7 (2 << 0)
2915 # define MR1_BITS_8 (3 << 0)
2916 # define MR1_PAR_EVN (0 << 2)
2917 # define MR1_PAR_ODD (1 << 2)
2918 # define MR1_PAR_NO (4 << 2)
2919 # define MR2_STOP1 (7 << 0)
2920 # define MR2_STOP2 (0xf << 0)
2921 #define SCCNXP_SR_REG (0x01)
2922 #define SCCNXP_CSR_REG SCCNXP_SR_REG
2923 # define SR_RXRDY (1 << 0)
2924 # define SR_FULL (1 << 1)
2925 # define SR_TXRDY (1 << 2)
2926 # define SR_TXEMT (1 << 3)
2927 # define SR_OVR (1 << 4)
2928 # define SR_PE (1 << 5)
2929 # define SR_FE (1 << 6)
2930 # define SR_BRK (1 << 7)
2931 #define SCCNXP_CR_REG (0x02)
2932 # define CR_RX_ENABLE (1 << 0)
2933 # define CR_RX_DISABLE (1 << 1)
2934 # define CR_TX_ENABLE (1 << 2)
2935 # define CR_TX_DISABLE (1 << 3)
2936 # define CR_CMD_MRPTR1 (0x01 << 4)
2937 # define CR_CMD_RX_RESET (0x02 << 4)
2938 # define CR_CMD_TX_RESET (0x03 << 4)
2939 # define CR_CMD_STATUS_RESET (0x04 << 4)
2940 # define CR_CMD_BREAK_RESET (0x05 << 4)
2941 # define CR_CMD_START_BREAK (0x06 << 4)
2942 # define CR_CMD_STOP_BREAK (0x07 << 4)
2943 # define CR_CMD_MRPTR0 (0x0b << 4)
2944 #define SCCNXP_RHR_REG (0x03)
2945 #define SCCNXP_THR_REG SCCNXP_RHR_REG
2946 #define SCCNXP_IPCR_REG (0x04)
2947 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
2948 # define ACR_BAUD0 (0 << 7)
2949 # define ACR_BAUD1 (1 << 7)
2950 # define ACR_TIMER_MODE (6 << 4)
2951 #define SCCNXP_ISR_REG (0x05)
2952 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
2953 # define IMR_TXRDY (1 << 0)
2954 # define IMR_RXRDY (1 << 1)
2955 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
2956 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
2957 #define SCCNXP_IPR_REG (0x0d)
2958 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
2959 #define SCCNXP_SOP_REG (0x0e)
2960 #define SCCNXP_ROP_REG (0x0f)
2961 #define MCTRL_MASK(sig) (0xf << (sig))
2962 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
2963 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
2964 #define SCCNXP_HAVE_IO 0x00000001
2965 #define SCCNXP_HAVE_MR0 0x00000002
2966 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2967 #endif
2968 /* LDV_COMMENT_END_PREP */
2969 /* LDV_COMMENT_FUNCTION_CALL Function from field "start_tx" from driver structure with callbacks "sccnxp_ops" */
2970 ldv_handler_precall();
2971 sccnxp_start_tx( var_group1);
2972 /* LDV_COMMENT_BEGIN_PREP */
2973 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2974 #endif
2975 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
2976 #endif
2977 /* LDV_COMMENT_END_PREP */
2978
2979
2980
2981
2982 }
2983
2984 break;
2985 case 5: {
2986
2987 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
2988
2989
2990 /* content: static void sccnxp_stop_rx(struct uart_port *port)*/
2991 /* LDV_COMMENT_BEGIN_PREP */
2992 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2993 #define SUPPORT_SYSRQ
2994 #endif
2995 #define SCCNXP_NAME "uart-sccnxp"
2996 #define SCCNXP_MAJOR 204
2997 #define SCCNXP_MINOR 205
2998 #define SCCNXP_MR_REG (0x00)
2999 # define MR0_BAUD_NORMAL (0 << 0)
3000 # define MR0_BAUD_EXT1 (1 << 0)
3001 # define MR0_BAUD_EXT2 (5 << 0)
3002 # define MR0_FIFO (1 << 3)
3003 # define MR0_TXLVL (1 << 4)
3004 # define MR1_BITS_5 (0 << 0)
3005 # define MR1_BITS_6 (1 << 0)
3006 # define MR1_BITS_7 (2 << 0)
3007 # define MR1_BITS_8 (3 << 0)
3008 # define MR1_PAR_EVN (0 << 2)
3009 # define MR1_PAR_ODD (1 << 2)
3010 # define MR1_PAR_NO (4 << 2)
3011 # define MR2_STOP1 (7 << 0)
3012 # define MR2_STOP2 (0xf << 0)
3013 #define SCCNXP_SR_REG (0x01)
3014 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3015 # define SR_RXRDY (1 << 0)
3016 # define SR_FULL (1 << 1)
3017 # define SR_TXRDY (1 << 2)
3018 # define SR_TXEMT (1 << 3)
3019 # define SR_OVR (1 << 4)
3020 # define SR_PE (1 << 5)
3021 # define SR_FE (1 << 6)
3022 # define SR_BRK (1 << 7)
3023 #define SCCNXP_CR_REG (0x02)
3024 # define CR_RX_ENABLE (1 << 0)
3025 # define CR_RX_DISABLE (1 << 1)
3026 # define CR_TX_ENABLE (1 << 2)
3027 # define CR_TX_DISABLE (1 << 3)
3028 # define CR_CMD_MRPTR1 (0x01 << 4)
3029 # define CR_CMD_RX_RESET (0x02 << 4)
3030 # define CR_CMD_TX_RESET (0x03 << 4)
3031 # define CR_CMD_STATUS_RESET (0x04 << 4)
3032 # define CR_CMD_BREAK_RESET (0x05 << 4)
3033 # define CR_CMD_START_BREAK (0x06 << 4)
3034 # define CR_CMD_STOP_BREAK (0x07 << 4)
3035 # define CR_CMD_MRPTR0 (0x0b << 4)
3036 #define SCCNXP_RHR_REG (0x03)
3037 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3038 #define SCCNXP_IPCR_REG (0x04)
3039 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3040 # define ACR_BAUD0 (0 << 7)
3041 # define ACR_BAUD1 (1 << 7)
3042 # define ACR_TIMER_MODE (6 << 4)
3043 #define SCCNXP_ISR_REG (0x05)
3044 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3045 # define IMR_TXRDY (1 << 0)
3046 # define IMR_RXRDY (1 << 1)
3047 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3048 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3049 #define SCCNXP_IPR_REG (0x0d)
3050 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3051 #define SCCNXP_SOP_REG (0x0e)
3052 #define SCCNXP_ROP_REG (0x0f)
3053 #define MCTRL_MASK(sig) (0xf << (sig))
3054 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3055 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3056 #define SCCNXP_HAVE_IO 0x00000001
3057 #define SCCNXP_HAVE_MR0 0x00000002
3058 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3059 #endif
3060 /* LDV_COMMENT_END_PREP */
3061 /* LDV_COMMENT_FUNCTION_CALL Function from field "stop_rx" from driver structure with callbacks "sccnxp_ops" */
3062 ldv_handler_precall();
3063 sccnxp_stop_rx( var_group1);
3064 /* LDV_COMMENT_BEGIN_PREP */
3065 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3066 #endif
3067 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3068 #endif
3069 /* LDV_COMMENT_END_PREP */
3070
3071
3072
3073
3074 }
3075
3076 break;
3077 case 6: {
3078
3079 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3080
3081
3082 /* content: static void sccnxp_break_ctl(struct uart_port *port, int break_state)*/
3083 /* LDV_COMMENT_BEGIN_PREP */
3084 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3085 #define SUPPORT_SYSRQ
3086 #endif
3087 #define SCCNXP_NAME "uart-sccnxp"
3088 #define SCCNXP_MAJOR 204
3089 #define SCCNXP_MINOR 205
3090 #define SCCNXP_MR_REG (0x00)
3091 # define MR0_BAUD_NORMAL (0 << 0)
3092 # define MR0_BAUD_EXT1 (1 << 0)
3093 # define MR0_BAUD_EXT2 (5 << 0)
3094 # define MR0_FIFO (1 << 3)
3095 # define MR0_TXLVL (1 << 4)
3096 # define MR1_BITS_5 (0 << 0)
3097 # define MR1_BITS_6 (1 << 0)
3098 # define MR1_BITS_7 (2 << 0)
3099 # define MR1_BITS_8 (3 << 0)
3100 # define MR1_PAR_EVN (0 << 2)
3101 # define MR1_PAR_ODD (1 << 2)
3102 # define MR1_PAR_NO (4 << 2)
3103 # define MR2_STOP1 (7 << 0)
3104 # define MR2_STOP2 (0xf << 0)
3105 #define SCCNXP_SR_REG (0x01)
3106 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3107 # define SR_RXRDY (1 << 0)
3108 # define SR_FULL (1 << 1)
3109 # define SR_TXRDY (1 << 2)
3110 # define SR_TXEMT (1 << 3)
3111 # define SR_OVR (1 << 4)
3112 # define SR_PE (1 << 5)
3113 # define SR_FE (1 << 6)
3114 # define SR_BRK (1 << 7)
3115 #define SCCNXP_CR_REG (0x02)
3116 # define CR_RX_ENABLE (1 << 0)
3117 # define CR_RX_DISABLE (1 << 1)
3118 # define CR_TX_ENABLE (1 << 2)
3119 # define CR_TX_DISABLE (1 << 3)
3120 # define CR_CMD_MRPTR1 (0x01 << 4)
3121 # define CR_CMD_RX_RESET (0x02 << 4)
3122 # define CR_CMD_TX_RESET (0x03 << 4)
3123 # define CR_CMD_STATUS_RESET (0x04 << 4)
3124 # define CR_CMD_BREAK_RESET (0x05 << 4)
3125 # define CR_CMD_START_BREAK (0x06 << 4)
3126 # define CR_CMD_STOP_BREAK (0x07 << 4)
3127 # define CR_CMD_MRPTR0 (0x0b << 4)
3128 #define SCCNXP_RHR_REG (0x03)
3129 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3130 #define SCCNXP_IPCR_REG (0x04)
3131 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3132 # define ACR_BAUD0 (0 << 7)
3133 # define ACR_BAUD1 (1 << 7)
3134 # define ACR_TIMER_MODE (6 << 4)
3135 #define SCCNXP_ISR_REG (0x05)
3136 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3137 # define IMR_TXRDY (1 << 0)
3138 # define IMR_RXRDY (1 << 1)
3139 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3140 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3141 #define SCCNXP_IPR_REG (0x0d)
3142 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3143 #define SCCNXP_SOP_REG (0x0e)
3144 #define SCCNXP_ROP_REG (0x0f)
3145 #define MCTRL_MASK(sig) (0xf << (sig))
3146 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3147 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3148 #define SCCNXP_HAVE_IO 0x00000001
3149 #define SCCNXP_HAVE_MR0 0x00000002
3150 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3151 #endif
3152 /* LDV_COMMENT_END_PREP */
3153 /* LDV_COMMENT_FUNCTION_CALL Function from field "break_ctl" from driver structure with callbacks "sccnxp_ops" */
3154 ldv_handler_precall();
3155 sccnxp_break_ctl( var_group1, var_sccnxp_break_ctl_20_p1);
3156 /* LDV_COMMENT_BEGIN_PREP */
3157 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3158 #endif
3159 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3160 #endif
3161 /* LDV_COMMENT_END_PREP */
3162
3163
3164
3165
3166 }
3167
3168 break;
3169 case 7: {
3170
3171 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3172
3173
3174 /* content: static int sccnxp_startup(struct uart_port *port)*/
3175 /* LDV_COMMENT_BEGIN_PREP */
3176 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3177 #define SUPPORT_SYSRQ
3178 #endif
3179 #define SCCNXP_NAME "uart-sccnxp"
3180 #define SCCNXP_MAJOR 204
3181 #define SCCNXP_MINOR 205
3182 #define SCCNXP_MR_REG (0x00)
3183 # define MR0_BAUD_NORMAL (0 << 0)
3184 # define MR0_BAUD_EXT1 (1 << 0)
3185 # define MR0_BAUD_EXT2 (5 << 0)
3186 # define MR0_FIFO (1 << 3)
3187 # define MR0_TXLVL (1 << 4)
3188 # define MR1_BITS_5 (0 << 0)
3189 # define MR1_BITS_6 (1 << 0)
3190 # define MR1_BITS_7 (2 << 0)
3191 # define MR1_BITS_8 (3 << 0)
3192 # define MR1_PAR_EVN (0 << 2)
3193 # define MR1_PAR_ODD (1 << 2)
3194 # define MR1_PAR_NO (4 << 2)
3195 # define MR2_STOP1 (7 << 0)
3196 # define MR2_STOP2 (0xf << 0)
3197 #define SCCNXP_SR_REG (0x01)
3198 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3199 # define SR_RXRDY (1 << 0)
3200 # define SR_FULL (1 << 1)
3201 # define SR_TXRDY (1 << 2)
3202 # define SR_TXEMT (1 << 3)
3203 # define SR_OVR (1 << 4)
3204 # define SR_PE (1 << 5)
3205 # define SR_FE (1 << 6)
3206 # define SR_BRK (1 << 7)
3207 #define SCCNXP_CR_REG (0x02)
3208 # define CR_RX_ENABLE (1 << 0)
3209 # define CR_RX_DISABLE (1 << 1)
3210 # define CR_TX_ENABLE (1 << 2)
3211 # define CR_TX_DISABLE (1 << 3)
3212 # define CR_CMD_MRPTR1 (0x01 << 4)
3213 # define CR_CMD_RX_RESET (0x02 << 4)
3214 # define CR_CMD_TX_RESET (0x03 << 4)
3215 # define CR_CMD_STATUS_RESET (0x04 << 4)
3216 # define CR_CMD_BREAK_RESET (0x05 << 4)
3217 # define CR_CMD_START_BREAK (0x06 << 4)
3218 # define CR_CMD_STOP_BREAK (0x07 << 4)
3219 # define CR_CMD_MRPTR0 (0x0b << 4)
3220 #define SCCNXP_RHR_REG (0x03)
3221 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3222 #define SCCNXP_IPCR_REG (0x04)
3223 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3224 # define ACR_BAUD0 (0 << 7)
3225 # define ACR_BAUD1 (1 << 7)
3226 # define ACR_TIMER_MODE (6 << 4)
3227 #define SCCNXP_ISR_REG (0x05)
3228 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3229 # define IMR_TXRDY (1 << 0)
3230 # define IMR_RXRDY (1 << 1)
3231 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3232 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3233 #define SCCNXP_IPR_REG (0x0d)
3234 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3235 #define SCCNXP_SOP_REG (0x0e)
3236 #define SCCNXP_ROP_REG (0x0f)
3237 #define MCTRL_MASK(sig) (0xf << (sig))
3238 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3239 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3240 #define SCCNXP_HAVE_IO 0x00000001
3241 #define SCCNXP_HAVE_MR0 0x00000002
3242 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3243 #endif
3244 /* LDV_COMMENT_END_PREP */
3245 /* LDV_COMMENT_FUNCTION_CALL Function from field "startup" from driver structure with callbacks "sccnxp_ops" */
3246 ldv_handler_precall();
3247 sccnxp_startup( var_group1);
3248 /* LDV_COMMENT_BEGIN_PREP */
3249 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3250 #endif
3251 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3252 #endif
3253 /* LDV_COMMENT_END_PREP */
3254
3255
3256
3257
3258 }
3259
3260 break;
3261 case 8: {
3262
3263 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3264
3265
3266 /* content: static void sccnxp_shutdown(struct uart_port *port)*/
3267 /* LDV_COMMENT_BEGIN_PREP */
3268 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3269 #define SUPPORT_SYSRQ
3270 #endif
3271 #define SCCNXP_NAME "uart-sccnxp"
3272 #define SCCNXP_MAJOR 204
3273 #define SCCNXP_MINOR 205
3274 #define SCCNXP_MR_REG (0x00)
3275 # define MR0_BAUD_NORMAL (0 << 0)
3276 # define MR0_BAUD_EXT1 (1 << 0)
3277 # define MR0_BAUD_EXT2 (5 << 0)
3278 # define MR0_FIFO (1 << 3)
3279 # define MR0_TXLVL (1 << 4)
3280 # define MR1_BITS_5 (0 << 0)
3281 # define MR1_BITS_6 (1 << 0)
3282 # define MR1_BITS_7 (2 << 0)
3283 # define MR1_BITS_8 (3 << 0)
3284 # define MR1_PAR_EVN (0 << 2)
3285 # define MR1_PAR_ODD (1 << 2)
3286 # define MR1_PAR_NO (4 << 2)
3287 # define MR2_STOP1 (7 << 0)
3288 # define MR2_STOP2 (0xf << 0)
3289 #define SCCNXP_SR_REG (0x01)
3290 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3291 # define SR_RXRDY (1 << 0)
3292 # define SR_FULL (1 << 1)
3293 # define SR_TXRDY (1 << 2)
3294 # define SR_TXEMT (1 << 3)
3295 # define SR_OVR (1 << 4)
3296 # define SR_PE (1 << 5)
3297 # define SR_FE (1 << 6)
3298 # define SR_BRK (1 << 7)
3299 #define SCCNXP_CR_REG (0x02)
3300 # define CR_RX_ENABLE (1 << 0)
3301 # define CR_RX_DISABLE (1 << 1)
3302 # define CR_TX_ENABLE (1 << 2)
3303 # define CR_TX_DISABLE (1 << 3)
3304 # define CR_CMD_MRPTR1 (0x01 << 4)
3305 # define CR_CMD_RX_RESET (0x02 << 4)
3306 # define CR_CMD_TX_RESET (0x03 << 4)
3307 # define CR_CMD_STATUS_RESET (0x04 << 4)
3308 # define CR_CMD_BREAK_RESET (0x05 << 4)
3309 # define CR_CMD_START_BREAK (0x06 << 4)
3310 # define CR_CMD_STOP_BREAK (0x07 << 4)
3311 # define CR_CMD_MRPTR0 (0x0b << 4)
3312 #define SCCNXP_RHR_REG (0x03)
3313 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3314 #define SCCNXP_IPCR_REG (0x04)
3315 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3316 # define ACR_BAUD0 (0 << 7)
3317 # define ACR_BAUD1 (1 << 7)
3318 # define ACR_TIMER_MODE (6 << 4)
3319 #define SCCNXP_ISR_REG (0x05)
3320 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3321 # define IMR_TXRDY (1 << 0)
3322 # define IMR_RXRDY (1 << 1)
3323 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3324 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3325 #define SCCNXP_IPR_REG (0x0d)
3326 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3327 #define SCCNXP_SOP_REG (0x0e)
3328 #define SCCNXP_ROP_REG (0x0f)
3329 #define MCTRL_MASK(sig) (0xf << (sig))
3330 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3331 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3332 #define SCCNXP_HAVE_IO 0x00000001
3333 #define SCCNXP_HAVE_MR0 0x00000002
3334 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3335 #endif
3336 /* LDV_COMMENT_END_PREP */
3337 /* LDV_COMMENT_FUNCTION_CALL Function from field "shutdown" from driver structure with callbacks "sccnxp_ops" */
3338 ldv_handler_precall();
3339 sccnxp_shutdown( var_group1);
3340 /* LDV_COMMENT_BEGIN_PREP */
3341 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3342 #endif
3343 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3344 #endif
3345 /* LDV_COMMENT_END_PREP */
3346
3347
3348
3349
3350 }
3351
3352 break;
3353 case 9: {
3354
3355 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3356
3357
3358 /* content: static void sccnxp_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)*/
3359 /* LDV_COMMENT_BEGIN_PREP */
3360 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3361 #define SUPPORT_SYSRQ
3362 #endif
3363 #define SCCNXP_NAME "uart-sccnxp"
3364 #define SCCNXP_MAJOR 204
3365 #define SCCNXP_MINOR 205
3366 #define SCCNXP_MR_REG (0x00)
3367 # define MR0_BAUD_NORMAL (0 << 0)
3368 # define MR0_BAUD_EXT1 (1 << 0)
3369 # define MR0_BAUD_EXT2 (5 << 0)
3370 # define MR0_FIFO (1 << 3)
3371 # define MR0_TXLVL (1 << 4)
3372 # define MR1_BITS_5 (0 << 0)
3373 # define MR1_BITS_6 (1 << 0)
3374 # define MR1_BITS_7 (2 << 0)
3375 # define MR1_BITS_8 (3 << 0)
3376 # define MR1_PAR_EVN (0 << 2)
3377 # define MR1_PAR_ODD (1 << 2)
3378 # define MR1_PAR_NO (4 << 2)
3379 # define MR2_STOP1 (7 << 0)
3380 # define MR2_STOP2 (0xf << 0)
3381 #define SCCNXP_SR_REG (0x01)
3382 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3383 # define SR_RXRDY (1 << 0)
3384 # define SR_FULL (1 << 1)
3385 # define SR_TXRDY (1 << 2)
3386 # define SR_TXEMT (1 << 3)
3387 # define SR_OVR (1 << 4)
3388 # define SR_PE (1 << 5)
3389 # define SR_FE (1 << 6)
3390 # define SR_BRK (1 << 7)
3391 #define SCCNXP_CR_REG (0x02)
3392 # define CR_RX_ENABLE (1 << 0)
3393 # define CR_RX_DISABLE (1 << 1)
3394 # define CR_TX_ENABLE (1 << 2)
3395 # define CR_TX_DISABLE (1 << 3)
3396 # define CR_CMD_MRPTR1 (0x01 << 4)
3397 # define CR_CMD_RX_RESET (0x02 << 4)
3398 # define CR_CMD_TX_RESET (0x03 << 4)
3399 # define CR_CMD_STATUS_RESET (0x04 << 4)
3400 # define CR_CMD_BREAK_RESET (0x05 << 4)
3401 # define CR_CMD_START_BREAK (0x06 << 4)
3402 # define CR_CMD_STOP_BREAK (0x07 << 4)
3403 # define CR_CMD_MRPTR0 (0x0b << 4)
3404 #define SCCNXP_RHR_REG (0x03)
3405 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3406 #define SCCNXP_IPCR_REG (0x04)
3407 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3408 # define ACR_BAUD0 (0 << 7)
3409 # define ACR_BAUD1 (1 << 7)
3410 # define ACR_TIMER_MODE (6 << 4)
3411 #define SCCNXP_ISR_REG (0x05)
3412 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3413 # define IMR_TXRDY (1 << 0)
3414 # define IMR_RXRDY (1 << 1)
3415 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3416 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3417 #define SCCNXP_IPR_REG (0x0d)
3418 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3419 #define SCCNXP_SOP_REG (0x0e)
3420 #define SCCNXP_ROP_REG (0x0f)
3421 #define MCTRL_MASK(sig) (0xf << (sig))
3422 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3423 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3424 #define SCCNXP_HAVE_IO 0x00000001
3425 #define SCCNXP_HAVE_MR0 0x00000002
3426 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3427 #endif
3428 /* LDV_COMMENT_END_PREP */
3429 /* LDV_COMMENT_FUNCTION_CALL Function from field "set_termios" from driver structure with callbacks "sccnxp_ops" */
3430 ldv_handler_precall();
3431 sccnxp_set_termios( var_group1, var_group2, var_sccnxp_set_termios_21_p2);
3432 /* LDV_COMMENT_BEGIN_PREP */
3433 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3434 #endif
3435 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3436 #endif
3437 /* LDV_COMMENT_END_PREP */
3438
3439
3440
3441
3442 }
3443
3444 break;
3445 case 10: {
3446
3447 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3448
3449
3450 /* content: static const char *sccnxp_type(struct uart_port *port)*/
3451 /* LDV_COMMENT_BEGIN_PREP */
3452 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3453 #define SUPPORT_SYSRQ
3454 #endif
3455 #define SCCNXP_NAME "uart-sccnxp"
3456 #define SCCNXP_MAJOR 204
3457 #define SCCNXP_MINOR 205
3458 #define SCCNXP_MR_REG (0x00)
3459 # define MR0_BAUD_NORMAL (0 << 0)
3460 # define MR0_BAUD_EXT1 (1 << 0)
3461 # define MR0_BAUD_EXT2 (5 << 0)
3462 # define MR0_FIFO (1 << 3)
3463 # define MR0_TXLVL (1 << 4)
3464 # define MR1_BITS_5 (0 << 0)
3465 # define MR1_BITS_6 (1 << 0)
3466 # define MR1_BITS_7 (2 << 0)
3467 # define MR1_BITS_8 (3 << 0)
3468 # define MR1_PAR_EVN (0 << 2)
3469 # define MR1_PAR_ODD (1 << 2)
3470 # define MR1_PAR_NO (4 << 2)
3471 # define MR2_STOP1 (7 << 0)
3472 # define MR2_STOP2 (0xf << 0)
3473 #define SCCNXP_SR_REG (0x01)
3474 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3475 # define SR_RXRDY (1 << 0)
3476 # define SR_FULL (1 << 1)
3477 # define SR_TXRDY (1 << 2)
3478 # define SR_TXEMT (1 << 3)
3479 # define SR_OVR (1 << 4)
3480 # define SR_PE (1 << 5)
3481 # define SR_FE (1 << 6)
3482 # define SR_BRK (1 << 7)
3483 #define SCCNXP_CR_REG (0x02)
3484 # define CR_RX_ENABLE (1 << 0)
3485 # define CR_RX_DISABLE (1 << 1)
3486 # define CR_TX_ENABLE (1 << 2)
3487 # define CR_TX_DISABLE (1 << 3)
3488 # define CR_CMD_MRPTR1 (0x01 << 4)
3489 # define CR_CMD_RX_RESET (0x02 << 4)
3490 # define CR_CMD_TX_RESET (0x03 << 4)
3491 # define CR_CMD_STATUS_RESET (0x04 << 4)
3492 # define CR_CMD_BREAK_RESET (0x05 << 4)
3493 # define CR_CMD_START_BREAK (0x06 << 4)
3494 # define CR_CMD_STOP_BREAK (0x07 << 4)
3495 # define CR_CMD_MRPTR0 (0x0b << 4)
3496 #define SCCNXP_RHR_REG (0x03)
3497 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3498 #define SCCNXP_IPCR_REG (0x04)
3499 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3500 # define ACR_BAUD0 (0 << 7)
3501 # define ACR_BAUD1 (1 << 7)
3502 # define ACR_TIMER_MODE (6 << 4)
3503 #define SCCNXP_ISR_REG (0x05)
3504 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3505 # define IMR_TXRDY (1 << 0)
3506 # define IMR_RXRDY (1 << 1)
3507 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3508 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3509 #define SCCNXP_IPR_REG (0x0d)
3510 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3511 #define SCCNXP_SOP_REG (0x0e)
3512 #define SCCNXP_ROP_REG (0x0f)
3513 #define MCTRL_MASK(sig) (0xf << (sig))
3514 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3515 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3516 #define SCCNXP_HAVE_IO 0x00000001
3517 #define SCCNXP_HAVE_MR0 0x00000002
3518 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3519 #endif
3520 /* LDV_COMMENT_END_PREP */
3521 /* LDV_COMMENT_FUNCTION_CALL Function from field "type" from driver structure with callbacks "sccnxp_ops" */
3522 ldv_handler_precall();
3523 sccnxp_type( var_group1);
3524 /* LDV_COMMENT_BEGIN_PREP */
3525 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3526 #endif
3527 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3528 #endif
3529 /* LDV_COMMENT_END_PREP */
3530
3531
3532
3533
3534 }
3535
3536 break;
3537 case 11: {
3538
3539 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3540
3541
3542 /* content: static void sccnxp_release_port(struct uart_port *port)*/
3543 /* LDV_COMMENT_BEGIN_PREP */
3544 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3545 #define SUPPORT_SYSRQ
3546 #endif
3547 #define SCCNXP_NAME "uart-sccnxp"
3548 #define SCCNXP_MAJOR 204
3549 #define SCCNXP_MINOR 205
3550 #define SCCNXP_MR_REG (0x00)
3551 # define MR0_BAUD_NORMAL (0 << 0)
3552 # define MR0_BAUD_EXT1 (1 << 0)
3553 # define MR0_BAUD_EXT2 (5 << 0)
3554 # define MR0_FIFO (1 << 3)
3555 # define MR0_TXLVL (1 << 4)
3556 # define MR1_BITS_5 (0 << 0)
3557 # define MR1_BITS_6 (1 << 0)
3558 # define MR1_BITS_7 (2 << 0)
3559 # define MR1_BITS_8 (3 << 0)
3560 # define MR1_PAR_EVN (0 << 2)
3561 # define MR1_PAR_ODD (1 << 2)
3562 # define MR1_PAR_NO (4 << 2)
3563 # define MR2_STOP1 (7 << 0)
3564 # define MR2_STOP2 (0xf << 0)
3565 #define SCCNXP_SR_REG (0x01)
3566 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3567 # define SR_RXRDY (1 << 0)
3568 # define SR_FULL (1 << 1)
3569 # define SR_TXRDY (1 << 2)
3570 # define SR_TXEMT (1 << 3)
3571 # define SR_OVR (1 << 4)
3572 # define SR_PE (1 << 5)
3573 # define SR_FE (1 << 6)
3574 # define SR_BRK (1 << 7)
3575 #define SCCNXP_CR_REG (0x02)
3576 # define CR_RX_ENABLE (1 << 0)
3577 # define CR_RX_DISABLE (1 << 1)
3578 # define CR_TX_ENABLE (1 << 2)
3579 # define CR_TX_DISABLE (1 << 3)
3580 # define CR_CMD_MRPTR1 (0x01 << 4)
3581 # define CR_CMD_RX_RESET (0x02 << 4)
3582 # define CR_CMD_TX_RESET (0x03 << 4)
3583 # define CR_CMD_STATUS_RESET (0x04 << 4)
3584 # define CR_CMD_BREAK_RESET (0x05 << 4)
3585 # define CR_CMD_START_BREAK (0x06 << 4)
3586 # define CR_CMD_STOP_BREAK (0x07 << 4)
3587 # define CR_CMD_MRPTR0 (0x0b << 4)
3588 #define SCCNXP_RHR_REG (0x03)
3589 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3590 #define SCCNXP_IPCR_REG (0x04)
3591 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3592 # define ACR_BAUD0 (0 << 7)
3593 # define ACR_BAUD1 (1 << 7)
3594 # define ACR_TIMER_MODE (6 << 4)
3595 #define SCCNXP_ISR_REG (0x05)
3596 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3597 # define IMR_TXRDY (1 << 0)
3598 # define IMR_RXRDY (1 << 1)
3599 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3600 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3601 #define SCCNXP_IPR_REG (0x0d)
3602 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3603 #define SCCNXP_SOP_REG (0x0e)
3604 #define SCCNXP_ROP_REG (0x0f)
3605 #define MCTRL_MASK(sig) (0xf << (sig))
3606 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3607 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3608 #define SCCNXP_HAVE_IO 0x00000001
3609 #define SCCNXP_HAVE_MR0 0x00000002
3610 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3611 #endif
3612 /* LDV_COMMENT_END_PREP */
3613 /* LDV_COMMENT_FUNCTION_CALL Function from field "release_port" from driver structure with callbacks "sccnxp_ops" */
3614 ldv_handler_precall();
3615 sccnxp_release_port( var_group1);
3616 /* LDV_COMMENT_BEGIN_PREP */
3617 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3618 #endif
3619 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3620 #endif
3621 /* LDV_COMMENT_END_PREP */
3622
3623
3624
3625
3626 }
3627
3628 break;
3629 case 12: {
3630
3631 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3632
3633
3634 /* content: static int sccnxp_request_port(struct uart_port *port)*/
3635 /* LDV_COMMENT_BEGIN_PREP */
3636 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3637 #define SUPPORT_SYSRQ
3638 #endif
3639 #define SCCNXP_NAME "uart-sccnxp"
3640 #define SCCNXP_MAJOR 204
3641 #define SCCNXP_MINOR 205
3642 #define SCCNXP_MR_REG (0x00)
3643 # define MR0_BAUD_NORMAL (0 << 0)
3644 # define MR0_BAUD_EXT1 (1 << 0)
3645 # define MR0_BAUD_EXT2 (5 << 0)
3646 # define MR0_FIFO (1 << 3)
3647 # define MR0_TXLVL (1 << 4)
3648 # define MR1_BITS_5 (0 << 0)
3649 # define MR1_BITS_6 (1 << 0)
3650 # define MR1_BITS_7 (2 << 0)
3651 # define MR1_BITS_8 (3 << 0)
3652 # define MR1_PAR_EVN (0 << 2)
3653 # define MR1_PAR_ODD (1 << 2)
3654 # define MR1_PAR_NO (4 << 2)
3655 # define MR2_STOP1 (7 << 0)
3656 # define MR2_STOP2 (0xf << 0)
3657 #define SCCNXP_SR_REG (0x01)
3658 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3659 # define SR_RXRDY (1 << 0)
3660 # define SR_FULL (1 << 1)
3661 # define SR_TXRDY (1 << 2)
3662 # define SR_TXEMT (1 << 3)
3663 # define SR_OVR (1 << 4)
3664 # define SR_PE (1 << 5)
3665 # define SR_FE (1 << 6)
3666 # define SR_BRK (1 << 7)
3667 #define SCCNXP_CR_REG (0x02)
3668 # define CR_RX_ENABLE (1 << 0)
3669 # define CR_RX_DISABLE (1 << 1)
3670 # define CR_TX_ENABLE (1 << 2)
3671 # define CR_TX_DISABLE (1 << 3)
3672 # define CR_CMD_MRPTR1 (0x01 << 4)
3673 # define CR_CMD_RX_RESET (0x02 << 4)
3674 # define CR_CMD_TX_RESET (0x03 << 4)
3675 # define CR_CMD_STATUS_RESET (0x04 << 4)
3676 # define CR_CMD_BREAK_RESET (0x05 << 4)
3677 # define CR_CMD_START_BREAK (0x06 << 4)
3678 # define CR_CMD_STOP_BREAK (0x07 << 4)
3679 # define CR_CMD_MRPTR0 (0x0b << 4)
3680 #define SCCNXP_RHR_REG (0x03)
3681 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3682 #define SCCNXP_IPCR_REG (0x04)
3683 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3684 # define ACR_BAUD0 (0 << 7)
3685 # define ACR_BAUD1 (1 << 7)
3686 # define ACR_TIMER_MODE (6 << 4)
3687 #define SCCNXP_ISR_REG (0x05)
3688 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3689 # define IMR_TXRDY (1 << 0)
3690 # define IMR_RXRDY (1 << 1)
3691 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3692 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3693 #define SCCNXP_IPR_REG (0x0d)
3694 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3695 #define SCCNXP_SOP_REG (0x0e)
3696 #define SCCNXP_ROP_REG (0x0f)
3697 #define MCTRL_MASK(sig) (0xf << (sig))
3698 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3699 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3700 #define SCCNXP_HAVE_IO 0x00000001
3701 #define SCCNXP_HAVE_MR0 0x00000002
3702 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3703 #endif
3704 /* LDV_COMMENT_END_PREP */
3705 /* LDV_COMMENT_FUNCTION_CALL Function from field "request_port" from driver structure with callbacks "sccnxp_ops" */
3706 ldv_handler_precall();
3707 sccnxp_request_port( var_group1);
3708 /* LDV_COMMENT_BEGIN_PREP */
3709 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3710 #endif
3711 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3712 #endif
3713 /* LDV_COMMENT_END_PREP */
3714
3715
3716
3717
3718 }
3719
3720 break;
3721 case 13: {
3722
3723 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3724
3725
3726 /* content: static void sccnxp_config_port(struct uart_port *port, int flags)*/
3727 /* LDV_COMMENT_BEGIN_PREP */
3728 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3729 #define SUPPORT_SYSRQ
3730 #endif
3731 #define SCCNXP_NAME "uart-sccnxp"
3732 #define SCCNXP_MAJOR 204
3733 #define SCCNXP_MINOR 205
3734 #define SCCNXP_MR_REG (0x00)
3735 # define MR0_BAUD_NORMAL (0 << 0)
3736 # define MR0_BAUD_EXT1 (1 << 0)
3737 # define MR0_BAUD_EXT2 (5 << 0)
3738 # define MR0_FIFO (1 << 3)
3739 # define MR0_TXLVL (1 << 4)
3740 # define MR1_BITS_5 (0 << 0)
3741 # define MR1_BITS_6 (1 << 0)
3742 # define MR1_BITS_7 (2 << 0)
3743 # define MR1_BITS_8 (3 << 0)
3744 # define MR1_PAR_EVN (0 << 2)
3745 # define MR1_PAR_ODD (1 << 2)
3746 # define MR1_PAR_NO (4 << 2)
3747 # define MR2_STOP1 (7 << 0)
3748 # define MR2_STOP2 (0xf << 0)
3749 #define SCCNXP_SR_REG (0x01)
3750 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3751 # define SR_RXRDY (1 << 0)
3752 # define SR_FULL (1 << 1)
3753 # define SR_TXRDY (1 << 2)
3754 # define SR_TXEMT (1 << 3)
3755 # define SR_OVR (1 << 4)
3756 # define SR_PE (1 << 5)
3757 # define SR_FE (1 << 6)
3758 # define SR_BRK (1 << 7)
3759 #define SCCNXP_CR_REG (0x02)
3760 # define CR_RX_ENABLE (1 << 0)
3761 # define CR_RX_DISABLE (1 << 1)
3762 # define CR_TX_ENABLE (1 << 2)
3763 # define CR_TX_DISABLE (1 << 3)
3764 # define CR_CMD_MRPTR1 (0x01 << 4)
3765 # define CR_CMD_RX_RESET (0x02 << 4)
3766 # define CR_CMD_TX_RESET (0x03 << 4)
3767 # define CR_CMD_STATUS_RESET (0x04 << 4)
3768 # define CR_CMD_BREAK_RESET (0x05 << 4)
3769 # define CR_CMD_START_BREAK (0x06 << 4)
3770 # define CR_CMD_STOP_BREAK (0x07 << 4)
3771 # define CR_CMD_MRPTR0 (0x0b << 4)
3772 #define SCCNXP_RHR_REG (0x03)
3773 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3774 #define SCCNXP_IPCR_REG (0x04)
3775 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3776 # define ACR_BAUD0 (0 << 7)
3777 # define ACR_BAUD1 (1 << 7)
3778 # define ACR_TIMER_MODE (6 << 4)
3779 #define SCCNXP_ISR_REG (0x05)
3780 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3781 # define IMR_TXRDY (1 << 0)
3782 # define IMR_RXRDY (1 << 1)
3783 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3784 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3785 #define SCCNXP_IPR_REG (0x0d)
3786 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3787 #define SCCNXP_SOP_REG (0x0e)
3788 #define SCCNXP_ROP_REG (0x0f)
3789 #define MCTRL_MASK(sig) (0xf << (sig))
3790 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3791 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3792 #define SCCNXP_HAVE_IO 0x00000001
3793 #define SCCNXP_HAVE_MR0 0x00000002
3794 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3795 #endif
3796 /* LDV_COMMENT_END_PREP */
3797 /* LDV_COMMENT_FUNCTION_CALL Function from field "config_port" from driver structure with callbacks "sccnxp_ops" */
3798 ldv_handler_precall();
3799 sccnxp_config_port( var_group1, var_sccnxp_config_port_27_p1);
3800 /* LDV_COMMENT_BEGIN_PREP */
3801 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3802 #endif
3803 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3804 #endif
3805 /* LDV_COMMENT_END_PREP */
3806
3807
3808
3809
3810 }
3811
3812 break;
3813 case 14: {
3814
3815 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/
3816
3817
3818 /* content: static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)*/
3819 /* LDV_COMMENT_BEGIN_PREP */
3820 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3821 #define SUPPORT_SYSRQ
3822 #endif
3823 #define SCCNXP_NAME "uart-sccnxp"
3824 #define SCCNXP_MAJOR 204
3825 #define SCCNXP_MINOR 205
3826 #define SCCNXP_MR_REG (0x00)
3827 # define MR0_BAUD_NORMAL (0 << 0)
3828 # define MR0_BAUD_EXT1 (1 << 0)
3829 # define MR0_BAUD_EXT2 (5 << 0)
3830 # define MR0_FIFO (1 << 3)
3831 # define MR0_TXLVL (1 << 4)
3832 # define MR1_BITS_5 (0 << 0)
3833 # define MR1_BITS_6 (1 << 0)
3834 # define MR1_BITS_7 (2 << 0)
3835 # define MR1_BITS_8 (3 << 0)
3836 # define MR1_PAR_EVN (0 << 2)
3837 # define MR1_PAR_ODD (1 << 2)
3838 # define MR1_PAR_NO (4 << 2)
3839 # define MR2_STOP1 (7 << 0)
3840 # define MR2_STOP2 (0xf << 0)
3841 #define SCCNXP_SR_REG (0x01)
3842 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3843 # define SR_RXRDY (1 << 0)
3844 # define SR_FULL (1 << 1)
3845 # define SR_TXRDY (1 << 2)
3846 # define SR_TXEMT (1 << 3)
3847 # define SR_OVR (1 << 4)
3848 # define SR_PE (1 << 5)
3849 # define SR_FE (1 << 6)
3850 # define SR_BRK (1 << 7)
3851 #define SCCNXP_CR_REG (0x02)
3852 # define CR_RX_ENABLE (1 << 0)
3853 # define CR_RX_DISABLE (1 << 1)
3854 # define CR_TX_ENABLE (1 << 2)
3855 # define CR_TX_DISABLE (1 << 3)
3856 # define CR_CMD_MRPTR1 (0x01 << 4)
3857 # define CR_CMD_RX_RESET (0x02 << 4)
3858 # define CR_CMD_TX_RESET (0x03 << 4)
3859 # define CR_CMD_STATUS_RESET (0x04 << 4)
3860 # define CR_CMD_BREAK_RESET (0x05 << 4)
3861 # define CR_CMD_START_BREAK (0x06 << 4)
3862 # define CR_CMD_STOP_BREAK (0x07 << 4)
3863 # define CR_CMD_MRPTR0 (0x0b << 4)
3864 #define SCCNXP_RHR_REG (0x03)
3865 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3866 #define SCCNXP_IPCR_REG (0x04)
3867 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3868 # define ACR_BAUD0 (0 << 7)
3869 # define ACR_BAUD1 (1 << 7)
3870 # define ACR_TIMER_MODE (6 << 4)
3871 #define SCCNXP_ISR_REG (0x05)
3872 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3873 # define IMR_TXRDY (1 << 0)
3874 # define IMR_RXRDY (1 << 1)
3875 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3876 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3877 #define SCCNXP_IPR_REG (0x0d)
3878 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3879 #define SCCNXP_SOP_REG (0x0e)
3880 #define SCCNXP_ROP_REG (0x0f)
3881 #define MCTRL_MASK(sig) (0xf << (sig))
3882 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3883 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3884 #define SCCNXP_HAVE_IO 0x00000001
3885 #define SCCNXP_HAVE_MR0 0x00000002
3886 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3887 #endif
3888 /* LDV_COMMENT_END_PREP */
3889 /* LDV_COMMENT_FUNCTION_CALL Function from field "verify_port" from driver structure with callbacks "sccnxp_ops" */
3890 ldv_handler_precall();
3891 sccnxp_verify_port( var_group1, var_group3);
3892 /* LDV_COMMENT_BEGIN_PREP */
3893 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3894 #endif
3895 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3896 #endif
3897 /* LDV_COMMENT_END_PREP */
3898
3899
3900
3901
3902 }
3903
3904 break;
3905 case 15: {
3906
3907 /** STRUCT: struct type: platform_driver, struct name: sccnxp_uart_driver **/
3908 if(ldv_s_sccnxp_uart_driver_platform_driver==0) {
3909
3910 /* content: static int sccnxp_probe(struct platform_device *pdev)*/
3911 /* LDV_COMMENT_BEGIN_PREP */
3912 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3913 #define SUPPORT_SYSRQ
3914 #endif
3915 #define SCCNXP_NAME "uart-sccnxp"
3916 #define SCCNXP_MAJOR 204
3917 #define SCCNXP_MINOR 205
3918 #define SCCNXP_MR_REG (0x00)
3919 # define MR0_BAUD_NORMAL (0 << 0)
3920 # define MR0_BAUD_EXT1 (1 << 0)
3921 # define MR0_BAUD_EXT2 (5 << 0)
3922 # define MR0_FIFO (1 << 3)
3923 # define MR0_TXLVL (1 << 4)
3924 # define MR1_BITS_5 (0 << 0)
3925 # define MR1_BITS_6 (1 << 0)
3926 # define MR1_BITS_7 (2 << 0)
3927 # define MR1_BITS_8 (3 << 0)
3928 # define MR1_PAR_EVN (0 << 2)
3929 # define MR1_PAR_ODD (1 << 2)
3930 # define MR1_PAR_NO (4 << 2)
3931 # define MR2_STOP1 (7 << 0)
3932 # define MR2_STOP2 (0xf << 0)
3933 #define SCCNXP_SR_REG (0x01)
3934 #define SCCNXP_CSR_REG SCCNXP_SR_REG
3935 # define SR_RXRDY (1 << 0)
3936 # define SR_FULL (1 << 1)
3937 # define SR_TXRDY (1 << 2)
3938 # define SR_TXEMT (1 << 3)
3939 # define SR_OVR (1 << 4)
3940 # define SR_PE (1 << 5)
3941 # define SR_FE (1 << 6)
3942 # define SR_BRK (1 << 7)
3943 #define SCCNXP_CR_REG (0x02)
3944 # define CR_RX_ENABLE (1 << 0)
3945 # define CR_RX_DISABLE (1 << 1)
3946 # define CR_TX_ENABLE (1 << 2)
3947 # define CR_TX_DISABLE (1 << 3)
3948 # define CR_CMD_MRPTR1 (0x01 << 4)
3949 # define CR_CMD_RX_RESET (0x02 << 4)
3950 # define CR_CMD_TX_RESET (0x03 << 4)
3951 # define CR_CMD_STATUS_RESET (0x04 << 4)
3952 # define CR_CMD_BREAK_RESET (0x05 << 4)
3953 # define CR_CMD_START_BREAK (0x06 << 4)
3954 # define CR_CMD_STOP_BREAK (0x07 << 4)
3955 # define CR_CMD_MRPTR0 (0x0b << 4)
3956 #define SCCNXP_RHR_REG (0x03)
3957 #define SCCNXP_THR_REG SCCNXP_RHR_REG
3958 #define SCCNXP_IPCR_REG (0x04)
3959 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
3960 # define ACR_BAUD0 (0 << 7)
3961 # define ACR_BAUD1 (1 << 7)
3962 # define ACR_TIMER_MODE (6 << 4)
3963 #define SCCNXP_ISR_REG (0x05)
3964 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
3965 # define IMR_TXRDY (1 << 0)
3966 # define IMR_RXRDY (1 << 1)
3967 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
3968 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
3969 #define SCCNXP_IPR_REG (0x0d)
3970 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
3971 #define SCCNXP_SOP_REG (0x0e)
3972 #define SCCNXP_ROP_REG (0x0f)
3973 #define MCTRL_MASK(sig) (0xf << (sig))
3974 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
3975 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
3976 #define SCCNXP_HAVE_IO 0x00000001
3977 #define SCCNXP_HAVE_MR0 0x00000002
3978 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3979 #endif
3980 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
3981 #endif
3982 /* LDV_COMMENT_END_PREP */
3983 /* LDV_COMMENT_FUNCTION_CALL Function from field "probe" from driver structure with callbacks "sccnxp_uart_driver". Standart function test for correct return result. */
3984 res_sccnxp_probe_32 = sccnxp_probe( var_group4);
3985 ldv_check_return_value(res_sccnxp_probe_32);
3986 ldv_check_return_value_probe(res_sccnxp_probe_32);
3987 if(res_sccnxp_probe_32)
3988 goto ldv_module_exit;
3989 ldv_s_sccnxp_uart_driver_platform_driver++;
3990
3991 }
3992
3993 }
3994
3995 break;
3996 case 16: {
3997
3998 /** STRUCT: struct type: platform_driver, struct name: sccnxp_uart_driver **/
3999 if(ldv_s_sccnxp_uart_driver_platform_driver==1) {
4000
4001 /* content: static int sccnxp_remove(struct platform_device *pdev)*/
4002 /* LDV_COMMENT_BEGIN_PREP */
4003 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
4004 #define SUPPORT_SYSRQ
4005 #endif
4006 #define SCCNXP_NAME "uart-sccnxp"
4007 #define SCCNXP_MAJOR 204
4008 #define SCCNXP_MINOR 205
4009 #define SCCNXP_MR_REG (0x00)
4010 # define MR0_BAUD_NORMAL (0 << 0)
4011 # define MR0_BAUD_EXT1 (1 << 0)
4012 # define MR0_BAUD_EXT2 (5 << 0)
4013 # define MR0_FIFO (1 << 3)
4014 # define MR0_TXLVL (1 << 4)
4015 # define MR1_BITS_5 (0 << 0)
4016 # define MR1_BITS_6 (1 << 0)
4017 # define MR1_BITS_7 (2 << 0)
4018 # define MR1_BITS_8 (3 << 0)
4019 # define MR1_PAR_EVN (0 << 2)
4020 # define MR1_PAR_ODD (1 << 2)
4021 # define MR1_PAR_NO (4 << 2)
4022 # define MR2_STOP1 (7 << 0)
4023 # define MR2_STOP2 (0xf << 0)
4024 #define SCCNXP_SR_REG (0x01)
4025 #define SCCNXP_CSR_REG SCCNXP_SR_REG
4026 # define SR_RXRDY (1 << 0)
4027 # define SR_FULL (1 << 1)
4028 # define SR_TXRDY (1 << 2)
4029 # define SR_TXEMT (1 << 3)
4030 # define SR_OVR (1 << 4)
4031 # define SR_PE (1 << 5)
4032 # define SR_FE (1 << 6)
4033 # define SR_BRK (1 << 7)
4034 #define SCCNXP_CR_REG (0x02)
4035 # define CR_RX_ENABLE (1 << 0)
4036 # define CR_RX_DISABLE (1 << 1)
4037 # define CR_TX_ENABLE (1 << 2)
4038 # define CR_TX_DISABLE (1 << 3)
4039 # define CR_CMD_MRPTR1 (0x01 << 4)
4040 # define CR_CMD_RX_RESET (0x02 << 4)
4041 # define CR_CMD_TX_RESET (0x03 << 4)
4042 # define CR_CMD_STATUS_RESET (0x04 << 4)
4043 # define CR_CMD_BREAK_RESET (0x05 << 4)
4044 # define CR_CMD_START_BREAK (0x06 << 4)
4045 # define CR_CMD_STOP_BREAK (0x07 << 4)
4046 # define CR_CMD_MRPTR0 (0x0b << 4)
4047 #define SCCNXP_RHR_REG (0x03)
4048 #define SCCNXP_THR_REG SCCNXP_RHR_REG
4049 #define SCCNXP_IPCR_REG (0x04)
4050 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
4051 # define ACR_BAUD0 (0 << 7)
4052 # define ACR_BAUD1 (1 << 7)
4053 # define ACR_TIMER_MODE (6 << 4)
4054 #define SCCNXP_ISR_REG (0x05)
4055 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
4056 # define IMR_TXRDY (1 << 0)
4057 # define IMR_RXRDY (1 << 1)
4058 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
4059 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
4060 #define SCCNXP_IPR_REG (0x0d)
4061 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
4062 #define SCCNXP_SOP_REG (0x0e)
4063 #define SCCNXP_ROP_REG (0x0f)
4064 #define MCTRL_MASK(sig) (0xf << (sig))
4065 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
4066 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
4067 #define SCCNXP_HAVE_IO 0x00000001
4068 #define SCCNXP_HAVE_MR0 0x00000002
4069 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4070 #endif
4071 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4072 #endif
4073 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4074 #endif
4075 /* LDV_COMMENT_END_PREP */
4076 /* LDV_COMMENT_FUNCTION_CALL Function from field "remove" from driver structure with callbacks "sccnxp_uart_driver" */
4077 ldv_handler_precall();
4078 sccnxp_remove( var_group4);
4079 ldv_s_sccnxp_uart_driver_platform_driver=0;
4080
4081 }
4082
4083 }
4084
4085 break;
4086 case 17: {
4087
4088 /** CALLBACK SECTION request_irq **/
4089 LDV_IN_INTERRUPT=2;
4090
4091 /* content: static irqreturn_t sccnxp_ist(int irq, void *dev_id)*/
4092 /* LDV_COMMENT_BEGIN_PREP */
4093 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
4094 #define SUPPORT_SYSRQ
4095 #endif
4096 #define SCCNXP_NAME "uart-sccnxp"
4097 #define SCCNXP_MAJOR 204
4098 #define SCCNXP_MINOR 205
4099 #define SCCNXP_MR_REG (0x00)
4100 # define MR0_BAUD_NORMAL (0 << 0)
4101 # define MR0_BAUD_EXT1 (1 << 0)
4102 # define MR0_BAUD_EXT2 (5 << 0)
4103 # define MR0_FIFO (1 << 3)
4104 # define MR0_TXLVL (1 << 4)
4105 # define MR1_BITS_5 (0 << 0)
4106 # define MR1_BITS_6 (1 << 0)
4107 # define MR1_BITS_7 (2 << 0)
4108 # define MR1_BITS_8 (3 << 0)
4109 # define MR1_PAR_EVN (0 << 2)
4110 # define MR1_PAR_ODD (1 << 2)
4111 # define MR1_PAR_NO (4 << 2)
4112 # define MR2_STOP1 (7 << 0)
4113 # define MR2_STOP2 (0xf << 0)
4114 #define SCCNXP_SR_REG (0x01)
4115 #define SCCNXP_CSR_REG SCCNXP_SR_REG
4116 # define SR_RXRDY (1 << 0)
4117 # define SR_FULL (1 << 1)
4118 # define SR_TXRDY (1 << 2)
4119 # define SR_TXEMT (1 << 3)
4120 # define SR_OVR (1 << 4)
4121 # define SR_PE (1 << 5)
4122 # define SR_FE (1 << 6)
4123 # define SR_BRK (1 << 7)
4124 #define SCCNXP_CR_REG (0x02)
4125 # define CR_RX_ENABLE (1 << 0)
4126 # define CR_RX_DISABLE (1 << 1)
4127 # define CR_TX_ENABLE (1 << 2)
4128 # define CR_TX_DISABLE (1 << 3)
4129 # define CR_CMD_MRPTR1 (0x01 << 4)
4130 # define CR_CMD_RX_RESET (0x02 << 4)
4131 # define CR_CMD_TX_RESET (0x03 << 4)
4132 # define CR_CMD_STATUS_RESET (0x04 << 4)
4133 # define CR_CMD_BREAK_RESET (0x05 << 4)
4134 # define CR_CMD_START_BREAK (0x06 << 4)
4135 # define CR_CMD_STOP_BREAK (0x07 << 4)
4136 # define CR_CMD_MRPTR0 (0x0b << 4)
4137 #define SCCNXP_RHR_REG (0x03)
4138 #define SCCNXP_THR_REG SCCNXP_RHR_REG
4139 #define SCCNXP_IPCR_REG (0x04)
4140 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
4141 # define ACR_BAUD0 (0 << 7)
4142 # define ACR_BAUD1 (1 << 7)
4143 # define ACR_TIMER_MODE (6 << 4)
4144 #define SCCNXP_ISR_REG (0x05)
4145 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
4146 # define IMR_TXRDY (1 << 0)
4147 # define IMR_RXRDY (1 << 1)
4148 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
4149 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
4150 #define SCCNXP_IPR_REG (0x0d)
4151 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
4152 #define SCCNXP_SOP_REG (0x0e)
4153 #define SCCNXP_ROP_REG (0x0f)
4154 #define MCTRL_MASK(sig) (0xf << (sig))
4155 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
4156 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
4157 #define SCCNXP_HAVE_IO 0x00000001
4158 #define SCCNXP_HAVE_MR0 0x00000002
4159 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4160 #endif
4161 /* LDV_COMMENT_END_PREP */
4162 /* LDV_COMMENT_FUNCTION_CALL */
4163 ldv_handler_precall();
4164 sccnxp_ist( var_sccnxp_ist_13_p0, var_sccnxp_ist_13_p1);
4165 /* LDV_COMMENT_BEGIN_PREP */
4166 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4167 #endif
4168 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
4169 #endif
4170 /* LDV_COMMENT_END_PREP */
4171 LDV_IN_INTERRUPT=1;
4172
4173
4174
4175 }
4176
4177 break;
4178 default: break;
4179
4180 }
4181
4182 }
4183
4184 ldv_module_exit:
4185
4186 /* LDV_COMMENT_FUNCTION_CALL Checks that all resources and locks are correctly released before the driver will be unloaded. */
4187 ldv_final: ldv_check_final_state();
4188
4189 /* LDV_COMMENT_END_FUNCTION_CALL_SECTION */
4190 return;
4191
4192 }
4193 #endif
4194
4195 /* LDV_COMMENT_END_MAIN */
4196
4197 #line 13 "/work/ldvuser/ref_launch/work/current--X--.--X--defaultlinux-4.13-rc1--X--320_7a--X--cpachecker/linux-4.13-rc1/csd_deg_dscv/4872/dscv_tempdir/dscv/ri/320_7a/drivers/tty/serial/sccnxp.o.c.prepared" 1
2 #include <verifier/rcv.h>
3 #include <kernel-model/ERR.inc>
4
5 struct clk;
6
7
8 /* LDV_COMMENT_CHANGE_STATE Initialize counter to zero. */
9 int ldv_counter_clk = 0;
10
11 /* LDV_COMMENT_MODEL_FUNCTION_DEFINITION(name='ldv_clk_disable_clk') Release. */
12 void ldv_clk_disable_clk(struct clk *clk)
13 {
14 /* LDV_COMMENT_CHANGE_STATE Increase counter. */
15 ldv_counter_clk = 0;
16 }
17
18 /* LDV_COMMENT_MODEL_FUNCTION_DEFINITION(name='ldv_clk_enable_clk') Reset counter. */
19 int ldv_clk_enable_clk(void)
20 {
21 int retval = ldv_undef_int();
22 if (!retval)
23 {
24 /* LDV_COMMENT_CHANGE_STATE Increase counter. */
25 ldv_counter_clk = 1;
26 }
27 return retval;
28 }
29
30
31 /* LDV_COMMENT_MODEL_FUNCTION_DEFINITION(name='ldv_check_final_state') Check that all clk are freed at the end */
32 void ldv_check_final_state(void)
33 {
34 /* LDV_COMMENT_ASSERT Spin 'clk' must be unlocked at the end */
35 ldv_assert(ldv_counter_clk == 0);
36 } 1 #ifndef _LDV_ERR_
2 #define _LDV_ERR_
3
4 #include <linux/kernel.h>
5
6 /* LDV_COMMENT_MODEL_FUNCTION_DEFENITION(name='ldv_is_err') This function return result of checking if pointer is impossible. */
7 bool ldv_is_err(const void *ptr)
8 {
9 /*LDV_COMMENT_RETURN Return value of function ldv_is_err_val().*/
10 return ((unsigned long)ptr > LDV_PTR_MAX);
11 }
12
13 /* LDV_COMMENT_MODEL_FUNCTION_DEFENITION(name='ldv_err_ptr') This function return pointer. */
14 void* ldv_err_ptr(long error)
15 {
16 /*LDV_COMMENT_RETURN Return error pointer.*/
17 return (void *)(LDV_PTR_MAX - error);
18 }
19
20 /* LDV_COMMENT_MODEL_FUNCTION_DEFENITION(name='ldv_ptr_err') This function return error if pointer is impossible. */
21 long ldv_ptr_err(const void *ptr)
22 {
23 /*LDV_COMMENT_RETURN Return error code.*/
24 return (long)(LDV_PTR_MAX - (unsigned long)ptr);
25 }
26
27 /* LDV_COMMENT_MODEL_FUNCTION_DEFENITION(name='ldv_is_err_or_null') This function check if pointer is impossible or null. */
28 bool ldv_is_err_or_null(const void *ptr)
29 {
30 /*LDV_COMMENT_RETURN Return 0 if pointer is possible and not zero, and 1 in other cases*/
31 return !ptr || ldv_is_err((unsigned long)ptr);
32 }
33
34 #endif /* _LDV_ERR_ */ 1 #ifndef _LDV_RCV_H_
2 #define _LDV_RCV_H_
3
4 /* If expr evaluates to zero, ldv_assert() causes a program to reach the error
5 label like the standard assert(). */
6 #define ldv_assert(expr) ((expr) ? 0 : ldv_error())
7
8 /* The error label wrapper. It is used because of some static verifiers (like
9 BLAST) don't accept multiple error labels through a program. */
10 static inline void ldv_error(void)
11 {
12 LDV_ERROR: goto LDV_ERROR;
13 }
14
15 /* If expr evaluates to zero, ldv_assume() causes an infinite loop that is
16 avoided by verifiers. */
17 #define ldv_assume(expr) ((expr) ? 0 : ldv_stop())
18
19 /* Infinite loop, that causes verifiers to skip such paths. */
20 static inline void ldv_stop(void) {
21 LDV_STOP: goto LDV_STOP;
22 }
23
24 /* Special nondeterministic functions. */
25 int ldv_undef_int(void);
26 void *ldv_undef_ptr(void);
27 unsigned long ldv_undef_ulong(void);
28 long ldv_undef_long(void);
29 /* Return nondeterministic negative integer number. */
30 static inline int ldv_undef_int_negative(void)
31 {
32 int ret = ldv_undef_int();
33
34 ldv_assume(ret < 0);
35
36 return ret;
37 }
38 /* Return nondeterministic nonpositive integer number. */
39 static inline int ldv_undef_int_nonpositive(void)
40 {
41 int ret = ldv_undef_int();
42
43 ldv_assume(ret <= 0);
44
45 return ret;
46 }
47
48 /* Add explicit model for __builin_expect GCC function. Without the model a
49 return value will be treated as nondetermined by verifiers. */
50 static inline long __builtin_expect(long exp, long c)
51 {
52 return exp;
53 }
54
55 /* This function causes the program to exit abnormally. GCC implements this
56 function by using a target-dependent mechanism (such as intentionally executing
57 an illegal instruction) or by calling abort. The mechanism used may vary from
58 release to release so you should not rely on any particular implementation.
59 http://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html */
60 static inline void __builtin_trap(void)
61 {
62 ldv_assert(0);
63 }
64
65 /* The constant is for simulating an error of ldv_undef_ptr() function. */
66 #define LDV_PTR_MAX 2012
67
68 #endif /* _LDV_RCV_H_ */ 1 /*
2 * device.h - generic, centralized driver model
3 *
4 * Copyright (c) 2001-2003 Patrick Mochel <mochel@osdl.org>
5 * Copyright (c) 2004-2009 Greg Kroah-Hartman <gregkh@suse.de>
6 * Copyright (c) 2008-2009 Novell Inc.
7 *
8 * This file is released under the GPLv2
9 *
10 * See Documentation/driver-model/ for more information.
11 */
12
13 #ifndef _DEVICE_H_
14 #define _DEVICE_H_
15
16 #include <linux/ioport.h>
17 #include <linux/kobject.h>
18 #include <linux/klist.h>
19 #include <linux/list.h>
20 #include <linux/lockdep.h>
21 #include <linux/compiler.h>
22 #include <linux/types.h>
23 #include <linux/mutex.h>
24 #include <linux/pinctrl/devinfo.h>
25 #include <linux/pm.h>
26 #include <linux/atomic.h>
27 #include <linux/ratelimit.h>
28 #include <linux/uidgid.h>
29 #include <linux/gfp.h>
30 #include <asm/device.h>
31
32 struct device;
33 struct device_private;
34 struct device_driver;
35 struct driver_private;
36 struct module;
37 struct class;
38 struct subsys_private;
39 struct bus_type;
40 struct device_node;
41 struct fwnode_handle;
42 struct iommu_ops;
43 struct iommu_group;
44 struct iommu_fwspec;
45
46 struct bus_attribute {
47 struct attribute attr;
48 ssize_t (*show)(struct bus_type *bus, char *buf);
49 ssize_t (*store)(struct bus_type *bus, const char *buf, size_t count);
50 };
51
52 #define BUS_ATTR(_name, _mode, _show, _store) \
53 struct bus_attribute bus_attr_##_name = __ATTR(_name, _mode, _show, _store)
54 #define BUS_ATTR_RW(_name) \
55 struct bus_attribute bus_attr_##_name = __ATTR_RW(_name)
56 #define BUS_ATTR_RO(_name) \
57 struct bus_attribute bus_attr_##_name = __ATTR_RO(_name)
58
59 extern int __must_check bus_create_file(struct bus_type *,
60 struct bus_attribute *);
61 extern void bus_remove_file(struct bus_type *, struct bus_attribute *);
62
63 /**
64 * struct bus_type - The bus type of the device
65 *
66 * @name: The name of the bus.
67 * @dev_name: Used for subsystems to enumerate devices like ("foo%u", dev->id).
68 * @dev_root: Default device to use as the parent.
69 * @bus_groups: Default attributes of the bus.
70 * @dev_groups: Default attributes of the devices on the bus.
71 * @drv_groups: Default attributes of the device drivers on the bus.
72 * @match: Called, perhaps multiple times, whenever a new device or driver
73 * is added for this bus. It should return a positive value if the
74 * given device can be handled by the given driver and zero
75 * otherwise. It may also return error code if determining that
76 * the driver supports the device is not possible. In case of
77 * -EPROBE_DEFER it will queue the device for deferred probing.
78 * @uevent: Called when a device is added, removed, or a few other things
79 * that generate uevents to add the environment variables.
80 * @probe: Called when a new device or driver add to this bus, and callback
81 * the specific driver's probe to initial the matched device.
82 * @remove: Called when a device removed from this bus.
83 * @shutdown: Called at shut-down time to quiesce the device.
84 *
85 * @online: Called to put the device back online (after offlining it).
86 * @offline: Called to put the device offline for hot-removal. May fail.
87 *
88 * @suspend: Called when a device on this bus wants to go to sleep mode.
89 * @resume: Called to bring a device on this bus out of sleep mode.
90 * @num_vf: Called to find out how many virtual functions a device on this
91 * bus supports.
92 * @pm: Power management operations of this bus, callback the specific
93 * device driver's pm-ops.
94 * @iommu_ops: IOMMU specific operations for this bus, used to attach IOMMU
95 * driver implementations to a bus and allow the driver to do
96 * bus-specific setup
97 * @p: The private data of the driver core, only the driver core can
98 * touch this.
99 * @lock_key: Lock class key for use by the lock validator
100 *
101 * A bus is a channel between the processor and one or more devices. For the
102 * purposes of the device model, all devices are connected via a bus, even if
103 * it is an internal, virtual, "platform" bus. Buses can plug into each other.
104 * A USB controller is usually a PCI device, for example. The device model
105 * represents the actual connections between buses and the devices they control.
106 * A bus is represented by the bus_type structure. It contains the name, the
107 * default attributes, the bus' methods, PM operations, and the driver core's
108 * private data.
109 */
110 struct bus_type {
111 const char *name;
112 const char *dev_name;
113 struct device *dev_root;
114 const struct attribute_group **bus_groups;
115 const struct attribute_group **dev_groups;
116 const struct attribute_group **drv_groups;
117
118 int (*match)(struct device *dev, struct device_driver *drv);
119 int (*uevent)(struct device *dev, struct kobj_uevent_env *env);
120 int (*probe)(struct device *dev);
121 int (*remove)(struct device *dev);
122 void (*shutdown)(struct device *dev);
123
124 int (*online)(struct device *dev);
125 int (*offline)(struct device *dev);
126
127 int (*suspend)(struct device *dev, pm_message_t state);
128 int (*resume)(struct device *dev);
129
130 int (*num_vf)(struct device *dev);
131
132 const struct dev_pm_ops *pm;
133
134 const struct iommu_ops *iommu_ops;
135
136 struct subsys_private *p;
137 struct lock_class_key lock_key;
138 };
139
140 extern int __must_check bus_register(struct bus_type *bus);
141
142 extern void bus_unregister(struct bus_type *bus);
143
144 extern int __must_check bus_rescan_devices(struct bus_type *bus);
145
146 /* iterator helpers for buses */
147 struct subsys_dev_iter {
148 struct klist_iter ki;
149 const struct device_type *type;
150 };
151 void subsys_dev_iter_init(struct subsys_dev_iter *iter,
152 struct bus_type *subsys,
153 struct device *start,
154 const struct device_type *type);
155 struct device *subsys_dev_iter_next(struct subsys_dev_iter *iter);
156 void subsys_dev_iter_exit(struct subsys_dev_iter *iter);
157
158 int bus_for_each_dev(struct bus_type *bus, struct device *start, void *data,
159 int (*fn)(struct device *dev, void *data));
160 struct device *bus_find_device(struct bus_type *bus, struct device *start,
161 void *data,
162 int (*match)(struct device *dev, void *data));
163 struct device *bus_find_device_by_name(struct bus_type *bus,
164 struct device *start,
165 const char *name);
166 struct device *subsys_find_device_by_id(struct bus_type *bus, unsigned int id,
167 struct device *hint);
168 int bus_for_each_drv(struct bus_type *bus, struct device_driver *start,
169 void *data, int (*fn)(struct device_driver *, void *));
170 void bus_sort_breadthfirst(struct bus_type *bus,
171 int (*compare)(const struct device *a,
172 const struct device *b));
173 /*
174 * Bus notifiers: Get notified of addition/removal of devices
175 * and binding/unbinding of drivers to devices.
176 * In the long run, it should be a replacement for the platform
177 * notify hooks.
178 */
179 struct notifier_block;
180
181 extern int bus_register_notifier(struct bus_type *bus,
182 struct notifier_block *nb);
183 extern int bus_unregister_notifier(struct bus_type *bus,
184 struct notifier_block *nb);
185
186 /* All 4 notifers below get called with the target struct device *
187 * as an argument. Note that those functions are likely to be called
188 * with the device lock held in the core, so be careful.
189 */
190 #define BUS_NOTIFY_ADD_DEVICE 0x00000001 /* device added */
191 #define BUS_NOTIFY_DEL_DEVICE 0x00000002 /* device to be removed */
192 #define BUS_NOTIFY_REMOVED_DEVICE 0x00000003 /* device removed */
193 #define BUS_NOTIFY_BIND_DRIVER 0x00000004 /* driver about to be
194 bound */
195 #define BUS_NOTIFY_BOUND_DRIVER 0x00000005 /* driver bound to device */
196 #define BUS_NOTIFY_UNBIND_DRIVER 0x00000006 /* driver about to be
197 unbound */
198 #define BUS_NOTIFY_UNBOUND_DRIVER 0x00000007 /* driver is unbound
199 from the device */
200 #define BUS_NOTIFY_DRIVER_NOT_BOUND 0x00000008 /* driver fails to be bound */
201
202 extern struct kset *bus_get_kset(struct bus_type *bus);
203 extern struct klist *bus_get_device_klist(struct bus_type *bus);
204
205 /**
206 * enum probe_type - device driver probe type to try
207 * Device drivers may opt in for special handling of their
208 * respective probe routines. This tells the core what to
209 * expect and prefer.
210 *
211 * @PROBE_DEFAULT_STRATEGY: Used by drivers that work equally well
212 * whether probed synchronously or asynchronously.
213 * @PROBE_PREFER_ASYNCHRONOUS: Drivers for "slow" devices which
214 * probing order is not essential for booting the system may
215 * opt into executing their probes asynchronously.
216 * @PROBE_FORCE_SYNCHRONOUS: Use this to annotate drivers that need
217 * their probe routines to run synchronously with driver and
218 * device registration (with the exception of -EPROBE_DEFER
219 * handling - re-probing always ends up being done asynchronously).
220 *
221 * Note that the end goal is to switch the kernel to use asynchronous
222 * probing by default, so annotating drivers with
223 * %PROBE_PREFER_ASYNCHRONOUS is a temporary measure that allows us
224 * to speed up boot process while we are validating the rest of the
225 * drivers.
226 */
227 enum probe_type {
228 PROBE_DEFAULT_STRATEGY,
229 PROBE_PREFER_ASYNCHRONOUS,
230 PROBE_FORCE_SYNCHRONOUS,
231 };
232
233 /**
234 * struct device_driver - The basic device driver structure
235 * @name: Name of the device driver.
236 * @bus: The bus which the device of this driver belongs to.
237 * @owner: The module owner.
238 * @mod_name: Used for built-in modules.
239 * @suppress_bind_attrs: Disables bind/unbind via sysfs.
240 * @probe_type: Type of the probe (synchronous or asynchronous) to use.
241 * @of_match_table: The open firmware table.
242 * @acpi_match_table: The ACPI match table.
243 * @probe: Called to query the existence of a specific device,
244 * whether this driver can work with it, and bind the driver
245 * to a specific device.
246 * @remove: Called when the device is removed from the system to
247 * unbind a device from this driver.
248 * @shutdown: Called at shut-down time to quiesce the device.
249 * @suspend: Called to put the device to sleep mode. Usually to a
250 * low power state.
251 * @resume: Called to bring a device from sleep mode.
252 * @groups: Default attributes that get created by the driver core
253 * automatically.
254 * @pm: Power management operations of the device which matched
255 * this driver.
256 * @p: Driver core's private data, no one other than the driver
257 * core can touch this.
258 *
259 * The device driver-model tracks all of the drivers known to the system.
260 * The main reason for this tracking is to enable the driver core to match
261 * up drivers with new devices. Once drivers are known objects within the
262 * system, however, a number of other things become possible. Device drivers
263 * can export information and configuration variables that are independent
264 * of any specific device.
265 */
266 struct device_driver {
267 const char *name;
268 struct bus_type *bus;
269
270 struct module *owner;
271 const char *mod_name; /* used for built-in modules */
272
273 bool suppress_bind_attrs; /* disables bind/unbind via sysfs */
274 enum probe_type probe_type;
275
276 const struct of_device_id *of_match_table;
277 const struct acpi_device_id *acpi_match_table;
278
279 int (*probe) (struct device *dev);
280 int (*remove) (struct device *dev);
281 void (*shutdown) (struct device *dev);
282 int (*suspend) (struct device *dev, pm_message_t state);
283 int (*resume) (struct device *dev);
284 const struct attribute_group **groups;
285
286 const struct dev_pm_ops *pm;
287
288 struct driver_private *p;
289 };
290
291
292 extern int __must_check driver_register(struct device_driver *drv);
293 extern void driver_unregister(struct device_driver *drv);
294
295 extern struct device_driver *driver_find(const char *name,
296 struct bus_type *bus);
297 extern int driver_probe_done(void);
298 extern void wait_for_device_probe(void);
299
300
301 /* sysfs interface for exporting driver attributes */
302
303 struct driver_attribute {
304 struct attribute attr;
305 ssize_t (*show)(struct device_driver *driver, char *buf);
306 ssize_t (*store)(struct device_driver *driver, const char *buf,
307 size_t count);
308 };
309
310 #define DRIVER_ATTR(_name, _mode, _show, _store) \
311 struct driver_attribute driver_attr_##_name = __ATTR(_name, _mode, _show, _store)
312 #define DRIVER_ATTR_RW(_name) \
313 struct driver_attribute driver_attr_##_name = __ATTR_RW(_name)
314 #define DRIVER_ATTR_RO(_name) \
315 struct driver_attribute driver_attr_##_name = __ATTR_RO(_name)
316 #define DRIVER_ATTR_WO(_name) \
317 struct driver_attribute driver_attr_##_name = __ATTR_WO(_name)
318
319 extern int __must_check driver_create_file(struct device_driver *driver,
320 const struct driver_attribute *attr);
321 extern void driver_remove_file(struct device_driver *driver,
322 const struct driver_attribute *attr);
323
324 extern int __must_check driver_for_each_device(struct device_driver *drv,
325 struct device *start,
326 void *data,
327 int (*fn)(struct device *dev,
328 void *));
329 struct device *driver_find_device(struct device_driver *drv,
330 struct device *start, void *data,
331 int (*match)(struct device *dev, void *data));
332
333 /**
334 * struct subsys_interface - interfaces to device functions
335 * @name: name of the device function
336 * @subsys: subsytem of the devices to attach to
337 * @node: the list of functions registered at the subsystem
338 * @add_dev: device hookup to device function handler
339 * @remove_dev: device hookup to device function handler
340 *
341 * Simple interfaces attached to a subsystem. Multiple interfaces can
342 * attach to a subsystem and its devices. Unlike drivers, they do not
343 * exclusively claim or control devices. Interfaces usually represent
344 * a specific functionality of a subsystem/class of devices.
345 */
346 struct subsys_interface {
347 const char *name;
348 struct bus_type *subsys;
349 struct list_head node;
350 int (*add_dev)(struct device *dev, struct subsys_interface *sif);
351 void (*remove_dev)(struct device *dev, struct subsys_interface *sif);
352 };
353
354 int subsys_interface_register(struct subsys_interface *sif);
355 void subsys_interface_unregister(struct subsys_interface *sif);
356
357 int subsys_system_register(struct bus_type *subsys,
358 const struct attribute_group **groups);
359 int subsys_virtual_register(struct bus_type *subsys,
360 const struct attribute_group **groups);
361
362 /**
363 * struct class - device classes
364 * @name: Name of the class.
365 * @owner: The module owner.
366 * @class_groups: Default attributes of this class.
367 * @dev_groups: Default attributes of the devices that belong to the class.
368 * @dev_kobj: The kobject that represents this class and links it into the hierarchy.
369 * @dev_uevent: Called when a device is added, removed from this class, or a
370 * few other things that generate uevents to add the environment
371 * variables.
372 * @devnode: Callback to provide the devtmpfs.
373 * @class_release: Called to release this class.
374 * @dev_release: Called to release the device.
375 * @suspend: Used to put the device to sleep mode, usually to a low power
376 * state.
377 * @resume: Used to bring the device from the sleep mode.
378 * @shutdown: Called at shut-down time to quiesce the device.
379 * @ns_type: Callbacks so sysfs can detemine namespaces.
380 * @namespace: Namespace of the device belongs to this class.
381 * @pm: The default device power management operations of this class.
382 * @p: The private data of the driver core, no one other than the
383 * driver core can touch this.
384 *
385 * A class is a higher-level view of a device that abstracts out low-level
386 * implementation details. Drivers may see a SCSI disk or an ATA disk, but,
387 * at the class level, they are all simply disks. Classes allow user space
388 * to work with devices based on what they do, rather than how they are
389 * connected or how they work.
390 */
391 struct class {
392 const char *name;
393 struct module *owner;
394
395 const struct attribute_group **class_groups;
396 const struct attribute_group **dev_groups;
397 struct kobject *dev_kobj;
398
399 int (*dev_uevent)(struct device *dev, struct kobj_uevent_env *env);
400 char *(*devnode)(struct device *dev, umode_t *mode);
401
402 void (*class_release)(struct class *class);
403 void (*dev_release)(struct device *dev);
404
405 int (*suspend)(struct device *dev, pm_message_t state);
406 int (*resume)(struct device *dev);
407 int (*shutdown)(struct device *dev);
408
409 const struct kobj_ns_type_operations *ns_type;
410 const void *(*namespace)(struct device *dev);
411
412 const struct dev_pm_ops *pm;
413
414 struct subsys_private *p;
415 };
416
417 struct class_dev_iter {
418 struct klist_iter ki;
419 const struct device_type *type;
420 };
421
422 extern struct kobject *sysfs_dev_block_kobj;
423 extern struct kobject *sysfs_dev_char_kobj;
424 extern int __must_check __class_register(struct class *class,
425 struct lock_class_key *key);
426 extern void class_unregister(struct class *class);
427
428 /* This is a #define to keep the compiler from merging different
429 * instances of the __key variable */
430 #define class_register(class) \
431 ({ \
432 static struct lock_class_key __key; \
433 __class_register(class, &__key); \
434 })
435
436 struct class_compat;
437 struct class_compat *class_compat_register(const char *name);
438 void class_compat_unregister(struct class_compat *cls);
439 int class_compat_create_link(struct class_compat *cls, struct device *dev,
440 struct device *device_link);
441 void class_compat_remove_link(struct class_compat *cls, struct device *dev,
442 struct device *device_link);
443
444 extern void class_dev_iter_init(struct class_dev_iter *iter,
445 struct class *class,
446 struct device *start,
447 const struct device_type *type);
448 extern struct device *class_dev_iter_next(struct class_dev_iter *iter);
449 extern void class_dev_iter_exit(struct class_dev_iter *iter);
450
451 extern int class_for_each_device(struct class *class, struct device *start,
452 void *data,
453 int (*fn)(struct device *dev, void *data));
454 extern struct device *class_find_device(struct class *class,
455 struct device *start, const void *data,
456 int (*match)(struct device *, const void *));
457
458 struct class_attribute {
459 struct attribute attr;
460 ssize_t (*show)(struct class *class, struct class_attribute *attr,
461 char *buf);
462 ssize_t (*store)(struct class *class, struct class_attribute *attr,
463 const char *buf, size_t count);
464 };
465
466 #define CLASS_ATTR_RW(_name) \
467 struct class_attribute class_attr_##_name = __ATTR_RW(_name)
468 #define CLASS_ATTR_RO(_name) \
469 struct class_attribute class_attr_##_name = __ATTR_RO(_name)
470 #define CLASS_ATTR_WO(_name) \
471 struct class_attribute class_attr_##_name = __ATTR_WO(_name)
472
473 extern int __must_check class_create_file_ns(struct class *class,
474 const struct class_attribute *attr,
475 const void *ns);
476 extern void class_remove_file_ns(struct class *class,
477 const struct class_attribute *attr,
478 const void *ns);
479
480 static inline int __must_check class_create_file(struct class *class,
481 const struct class_attribute *attr)
482 {
483 return class_create_file_ns(class, attr, NULL);
484 }
485
486 static inline void class_remove_file(struct class *class,
487 const struct class_attribute *attr)
488 {
489 return class_remove_file_ns(class, attr, NULL);
490 }
491
492 /* Simple class attribute that is just a static string */
493 struct class_attribute_string {
494 struct class_attribute attr;
495 char *str;
496 };
497
498 /* Currently read-only only */
499 #define _CLASS_ATTR_STRING(_name, _mode, _str) \
500 { __ATTR(_name, _mode, show_class_attr_string, NULL), _str }
501 #define CLASS_ATTR_STRING(_name, _mode, _str) \
502 struct class_attribute_string class_attr_##_name = \
503 _CLASS_ATTR_STRING(_name, _mode, _str)
504
505 extern ssize_t show_class_attr_string(struct class *class, struct class_attribute *attr,
506 char *buf);
507
508 struct class_interface {
509 struct list_head node;
510 struct class *class;
511
512 int (*add_dev) (struct device *, struct class_interface *);
513 void (*remove_dev) (struct device *, struct class_interface *);
514 };
515
516 extern int __must_check class_interface_register(struct class_interface *);
517 extern void class_interface_unregister(struct class_interface *);
518
519 extern struct class * __must_check __class_create(struct module *owner,
520 const char *name,
521 struct lock_class_key *key);
522 extern void class_destroy(struct class *cls);
523
524 /* This is a #define to keep the compiler from merging different
525 * instances of the __key variable */
526 #define class_create(owner, name) \
527 ({ \
528 static struct lock_class_key __key; \
529 __class_create(owner, name, &__key); \
530 })
531
532 /*
533 * The type of device, "struct device" is embedded in. A class
534 * or bus can contain devices of different types
535 * like "partitions" and "disks", "mouse" and "event".
536 * This identifies the device type and carries type-specific
537 * information, equivalent to the kobj_type of a kobject.
538 * If "name" is specified, the uevent will contain it in
539 * the DEVTYPE variable.
540 */
541 struct device_type {
542 const char *name;
543 const struct attribute_group **groups;
544 int (*uevent)(struct device *dev, struct kobj_uevent_env *env);
545 char *(*devnode)(struct device *dev, umode_t *mode,
546 kuid_t *uid, kgid_t *gid);
547 void (*release)(struct device *dev);
548
549 const struct dev_pm_ops *pm;
550 };
551
552 /* interface for exporting device attributes */
553 struct device_attribute {
554 struct attribute attr;
555 ssize_t (*show)(struct device *dev, struct device_attribute *attr,
556 char *buf);
557 ssize_t (*store)(struct device *dev, struct device_attribute *attr,
558 const char *buf, size_t count);
559 };
560
561 struct dev_ext_attribute {
562 struct device_attribute attr;
563 void *var;
564 };
565
566 ssize_t device_show_ulong(struct device *dev, struct device_attribute *attr,
567 char *buf);
568 ssize_t device_store_ulong(struct device *dev, struct device_attribute *attr,
569 const char *buf, size_t count);
570 ssize_t device_show_int(struct device *dev, struct device_attribute *attr,
571 char *buf);
572 ssize_t device_store_int(struct device *dev, struct device_attribute *attr,
573 const char *buf, size_t count);
574 ssize_t device_show_bool(struct device *dev, struct device_attribute *attr,
575 char *buf);
576 ssize_t device_store_bool(struct device *dev, struct device_attribute *attr,
577 const char *buf, size_t count);
578
579 #define DEVICE_ATTR(_name, _mode, _show, _store) \
580 struct device_attribute dev_attr_##_name = __ATTR(_name, _mode, _show, _store)
581 #define DEVICE_ATTR_RW(_name) \
582 struct device_attribute dev_attr_##_name = __ATTR_RW(_name)
583 #define DEVICE_ATTR_RO(_name) \
584 struct device_attribute dev_attr_##_name = __ATTR_RO(_name)
585 #define DEVICE_ATTR_WO(_name) \
586 struct device_attribute dev_attr_##_name = __ATTR_WO(_name)
587 #define DEVICE_ULONG_ATTR(_name, _mode, _var) \
588 struct dev_ext_attribute dev_attr_##_name = \
589 { __ATTR(_name, _mode, device_show_ulong, device_store_ulong), &(_var) }
590 #define DEVICE_INT_ATTR(_name, _mode, _var) \
591 struct dev_ext_attribute dev_attr_##_name = \
592 { __ATTR(_name, _mode, device_show_int, device_store_int), &(_var) }
593 #define DEVICE_BOOL_ATTR(_name, _mode, _var) \
594 struct dev_ext_attribute dev_attr_##_name = \
595 { __ATTR(_name, _mode, device_show_bool, device_store_bool), &(_var) }
596 #define DEVICE_ATTR_IGNORE_LOCKDEP(_name, _mode, _show, _store) \
597 struct device_attribute dev_attr_##_name = \
598 __ATTR_IGNORE_LOCKDEP(_name, _mode, _show, _store)
599
600 extern int device_create_file(struct device *device,
601 const struct device_attribute *entry);
602 extern void device_remove_file(struct device *dev,
603 const struct device_attribute *attr);
604 extern bool device_remove_file_self(struct device *dev,
605 const struct device_attribute *attr);
606 extern int __must_check device_create_bin_file(struct device *dev,
607 const struct bin_attribute *attr);
608 extern void device_remove_bin_file(struct device *dev,
609 const struct bin_attribute *attr);
610
611 /* device resource management */
612 typedef void (*dr_release_t)(struct device *dev, void *res);
613 typedef int (*dr_match_t)(struct device *dev, void *res, void *match_data);
614
615 #ifdef CONFIG_DEBUG_DEVRES
616 extern void *__devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp,
617 int nid, const char *name) __malloc;
618 #define devres_alloc(release, size, gfp) \
619 __devres_alloc_node(release, size, gfp, NUMA_NO_NODE, #release)
620 #define devres_alloc_node(release, size, gfp, nid) \
621 __devres_alloc_node(release, size, gfp, nid, #release)
622 #else
623 extern void *devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp,
624 int nid) __malloc;
625 static inline void *devres_alloc(dr_release_t release, size_t size, gfp_t gfp)
626 {
627 return devres_alloc_node(release, size, gfp, NUMA_NO_NODE);
628 }
629 #endif
630
631 extern void devres_for_each_res(struct device *dev, dr_release_t release,
632 dr_match_t match, void *match_data,
633 void (*fn)(struct device *, void *, void *),
634 void *data);
635 extern void devres_free(void *res);
636 extern void devres_add(struct device *dev, void *res);
637 extern void *devres_find(struct device *dev, dr_release_t release,
638 dr_match_t match, void *match_data);
639 extern void *devres_get(struct device *dev, void *new_res,
640 dr_match_t match, void *match_data);
641 extern void *devres_remove(struct device *dev, dr_release_t release,
642 dr_match_t match, void *match_data);
643 extern int devres_destroy(struct device *dev, dr_release_t release,
644 dr_match_t match, void *match_data);
645 extern int devres_release(struct device *dev, dr_release_t release,
646 dr_match_t match, void *match_data);
647
648 /* devres group */
649 extern void * __must_check devres_open_group(struct device *dev, void *id,
650 gfp_t gfp);
651 extern void devres_close_group(struct device *dev, void *id);
652 extern void devres_remove_group(struct device *dev, void *id);
653 extern int devres_release_group(struct device *dev, void *id);
654
655 /* managed devm_k.alloc/kfree for device drivers */
656 extern void *devm_kmalloc(struct device *dev, size_t size, gfp_t gfp) __malloc;
657 extern __printf(3, 0)
658 char *devm_kvasprintf(struct device *dev, gfp_t gfp, const char *fmt,
659 va_list ap) __malloc;
660 extern __printf(3, 4)
661 char *devm_kasprintf(struct device *dev, gfp_t gfp, const char *fmt, ...) __malloc;
662 static inline void *devm_kzalloc(struct device *dev, size_t size, gfp_t gfp)
663 {
664 return devm_kmalloc(dev, size, gfp | __GFP_ZERO);
665 }
666 static inline void *devm_kmalloc_array(struct device *dev,
667 size_t n, size_t size, gfp_t flags)
668 {
669 if (size != 0 && n > SIZE_MAX / size)
670 return NULL;
671 return devm_kmalloc(dev, n * size, flags);
672 }
673 static inline void *devm_kcalloc(struct device *dev,
674 size_t n, size_t size, gfp_t flags)
675 {
676 return devm_kmalloc_array(dev, n, size, flags | __GFP_ZERO);
677 }
678 extern void devm_kfree(struct device *dev, void *p);
679 extern char *devm_kstrdup(struct device *dev, const char *s, gfp_t gfp) __malloc;
680 extern void *devm_kmemdup(struct device *dev, const void *src, size_t len,
681 gfp_t gfp);
682
683 extern unsigned long devm_get_free_pages(struct device *dev,
684 gfp_t gfp_mask, unsigned int order);
685 extern void devm_free_pages(struct device *dev, unsigned long addr);
686
687 void __iomem *devm_ioremap_resource(struct device *dev, struct resource *res);
688
689 /* allows to add/remove a custom action to devres stack */
690 int devm_add_action(struct device *dev, void (*action)(void *), void *data);
691 void devm_remove_action(struct device *dev, void (*action)(void *), void *data);
692
693 static inline int devm_add_action_or_reset(struct device *dev,
694 void (*action)(void *), void *data)
695 {
696 int ret;
697
698 ret = devm_add_action(dev, action, data);
699 if (ret)
700 action(data);
701
702 return ret;
703 }
704
705 /**
706 * devm_alloc_percpu - Resource-managed alloc_percpu
707 * @dev: Device to allocate per-cpu memory for
708 * @type: Type to allocate per-cpu memory for
709 *
710 * Managed alloc_percpu. Per-cpu memory allocated with this function is
711 * automatically freed on driver detach.
712 *
713 * RETURNS:
714 * Pointer to allocated memory on success, NULL on failure.
715 */
716 #define devm_alloc_percpu(dev, type) \
717 ((typeof(type) __percpu *)__devm_alloc_percpu((dev), sizeof(type), \
718 __alignof__(type)))
719
720 void __percpu *__devm_alloc_percpu(struct device *dev, size_t size,
721 size_t align);
722 void devm_free_percpu(struct device *dev, void __percpu *pdata);
723
724 struct device_dma_parameters {
725 /*
726 * a low level driver may set these to teach IOMMU code about
727 * sg limitations.
728 */
729 unsigned int max_segment_size;
730 unsigned long segment_boundary_mask;
731 };
732
733 /**
734 * enum device_link_state - Device link states.
735 * @DL_STATE_NONE: The presence of the drivers is not being tracked.
736 * @DL_STATE_DORMANT: None of the supplier/consumer drivers is present.
737 * @DL_STATE_AVAILABLE: The supplier driver is present, but the consumer is not.
738 * @DL_STATE_CONSUMER_PROBE: The consumer is probing (supplier driver present).
739 * @DL_STATE_ACTIVE: Both the supplier and consumer drivers are present.
740 * @DL_STATE_SUPPLIER_UNBIND: The supplier driver is unbinding.
741 */
742 enum device_link_state {
743 DL_STATE_NONE = -1,
744 DL_STATE_DORMANT = 0,
745 DL_STATE_AVAILABLE,
746 DL_STATE_CONSUMER_PROBE,
747 DL_STATE_ACTIVE,
748 DL_STATE_SUPPLIER_UNBIND,
749 };
750
751 /*
752 * Device link flags.
753 *
754 * STATELESS: The core won't track the presence of supplier/consumer drivers.
755 * AUTOREMOVE: Remove this link automatically on consumer driver unbind.
756 * PM_RUNTIME: If set, the runtime PM framework will use this link.
757 * RPM_ACTIVE: Run pm_runtime_get_sync() on the supplier during link creation.
758 */
759 #define DL_FLAG_STATELESS BIT(0)
760 #define DL_FLAG_AUTOREMOVE BIT(1)
761 #define DL_FLAG_PM_RUNTIME BIT(2)
762 #define DL_FLAG_RPM_ACTIVE BIT(3)
763
764 /**
765 * struct device_link - Device link representation.
766 * @supplier: The device on the supplier end of the link.
767 * @s_node: Hook to the supplier device's list of links to consumers.
768 * @consumer: The device on the consumer end of the link.
769 * @c_node: Hook to the consumer device's list of links to suppliers.
770 * @status: The state of the link (with respect to the presence of drivers).
771 * @flags: Link flags.
772 * @rpm_active: Whether or not the consumer device is runtime-PM-active.
773 * @rcu_head: An RCU head to use for deferred execution of SRCU callbacks.
774 */
775 struct device_link {
776 struct device *supplier;
777 struct list_head s_node;
778 struct device *consumer;
779 struct list_head c_node;
780 enum device_link_state status;
781 u32 flags;
782 bool rpm_active;
783 #ifdef CONFIG_SRCU
784 struct rcu_head rcu_head;
785 #endif
786 };
787
788 /**
789 * enum dl_dev_state - Device driver presence tracking information.
790 * @DL_DEV_NO_DRIVER: There is no driver attached to the device.
791 * @DL_DEV_PROBING: A driver is probing.
792 * @DL_DEV_DRIVER_BOUND: The driver has been bound to the device.
793 * @DL_DEV_UNBINDING: The driver is unbinding from the device.
794 */
795 enum dl_dev_state {
796 DL_DEV_NO_DRIVER = 0,
797 DL_DEV_PROBING,
798 DL_DEV_DRIVER_BOUND,
799 DL_DEV_UNBINDING,
800 };
801
802 /**
803 * struct dev_links_info - Device data related to device links.
804 * @suppliers: List of links to supplier devices.
805 * @consumers: List of links to consumer devices.
806 * @status: Driver status information.
807 */
808 struct dev_links_info {
809 struct list_head suppliers;
810 struct list_head consumers;
811 enum dl_dev_state status;
812 };
813
814 /**
815 * struct device - The basic device structure
816 * @parent: The device's "parent" device, the device to which it is attached.
817 * In most cases, a parent device is some sort of bus or host
818 * controller. If parent is NULL, the device, is a top-level device,
819 * which is not usually what you want.
820 * @p: Holds the private data of the driver core portions of the device.
821 * See the comment of the struct device_private for detail.
822 * @kobj: A top-level, abstract class from which other classes are derived.
823 * @init_name: Initial name of the device.
824 * @type: The type of device.
825 * This identifies the device type and carries type-specific
826 * information.
827 * @mutex: Mutex to synchronize calls to its driver.
828 * @bus: Type of bus device is on.
829 * @driver: Which driver has allocated this
830 * @platform_data: Platform data specific to the device.
831 * Example: For devices on custom boards, as typical of embedded
832 * and SOC based hardware, Linux often uses platform_data to point
833 * to board-specific structures describing devices and how they
834 * are wired. That can include what ports are available, chip
835 * variants, which GPIO pins act in what additional roles, and so
836 * on. This shrinks the "Board Support Packages" (BSPs) and
837 * minimizes board-specific #ifdefs in drivers.
838 * @driver_data: Private pointer for driver specific info.
839 * @links: Links to suppliers and consumers of this device.
840 * @power: For device power management.
841 * See Documentation/power/admin-guide/devices.rst for details.
842 * @pm_domain: Provide callbacks that are executed during system suspend,
843 * hibernation, system resume and during runtime PM transitions
844 * along with subsystem-level and driver-level callbacks.
845 * @pins: For device pin management.
846 * See Documentation/pinctrl.txt for details.
847 * @msi_list: Hosts MSI descriptors
848 * @msi_domain: The generic MSI domain this device is using.
849 * @numa_node: NUMA node this device is close to.
850 * @dma_mask: Dma mask (if dma'ble device).
851 * @coherent_dma_mask: Like dma_mask, but for alloc_coherent mapping as not all
852 * hardware supports 64-bit addresses for consistent allocations
853 * such descriptors.
854 * @dma_pfn_offset: offset of DMA memory range relatively of RAM
855 * @dma_parms: A low level driver may set these to teach IOMMU code about
856 * segment limitations.
857 * @dma_pools: Dma pools (if dma'ble device).
858 * @dma_mem: Internal for coherent mem override.
859 * @cma_area: Contiguous memory area for dma allocations
860 * @archdata: For arch-specific additions.
861 * @of_node: Associated device tree node.
862 * @fwnode: Associated device node supplied by platform firmware.
863 * @devt: For creating the sysfs "dev".
864 * @id: device instance
865 * @devres_lock: Spinlock to protect the resource of the device.
866 * @devres_head: The resources list of the device.
867 * @knode_class: The node used to add the device to the class list.
868 * @class: The class of the device.
869 * @groups: Optional attribute groups.
870 * @release: Callback to free the device after all references have
871 * gone away. This should be set by the allocator of the
872 * device (i.e. the bus driver that discovered the device).
873 * @iommu_group: IOMMU group the device belongs to.
874 * @iommu_fwspec: IOMMU-specific properties supplied by firmware.
875 *
876 * @offline_disabled: If set, the device is permanently online.
877 * @offline: Set after successful invocation of bus type's .offline().
878 * @of_node_reused: Set if the device-tree node is shared with an ancestor
879 * device.
880 *
881 * At the lowest level, every device in a Linux system is represented by an
882 * instance of struct device. The device structure contains the information
883 * that the device model core needs to model the system. Most subsystems,
884 * however, track additional information about the devices they host. As a
885 * result, it is rare for devices to be represented by bare device structures;
886 * instead, that structure, like kobject structures, is usually embedded within
887 * a higher-level representation of the device.
888 */
889 struct device {
890 struct device *parent;
891
892 struct device_private *p;
893
894 struct kobject kobj;
895 const char *init_name; /* initial name of the device */
896 const struct device_type *type;
897
898 struct mutex mutex; /* mutex to synchronize calls to
899 * its driver.
900 */
901
902 struct bus_type *bus; /* type of bus device is on */
903 struct device_driver *driver; /* which driver has allocated this
904 device */
905 void *platform_data; /* Platform specific data, device
906 core doesn't touch it */
907 void *driver_data; /* Driver data, set and get with
908 dev_set/get_drvdata */
909 struct dev_links_info links;
910 struct dev_pm_info power;
911 struct dev_pm_domain *pm_domain;
912
913 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
914 struct irq_domain *msi_domain;
915 #endif
916 #ifdef CONFIG_PINCTRL
917 struct dev_pin_info *pins;
918 #endif
919 #ifdef CONFIG_GENERIC_MSI_IRQ
920 struct list_head msi_list;
921 #endif
922
923 #ifdef CONFIG_NUMA
924 int numa_node; /* NUMA node this device is close to */
925 #endif
926 const struct dma_map_ops *dma_ops;
927 u64 *dma_mask; /* dma mask (if dma'able device) */
928 u64 coherent_dma_mask;/* Like dma_mask, but for
929 alloc_coherent mappings as
930 not all hardware supports
931 64 bit addresses for consistent
932 allocations such descriptors. */
933 unsigned long dma_pfn_offset;
934
935 struct device_dma_parameters *dma_parms;
936
937 struct list_head dma_pools; /* dma pools (if dma'ble) */
938
939 struct dma_coherent_mem *dma_mem; /* internal for coherent mem
940 override */
941 #ifdef CONFIG_DMA_CMA
942 struct cma *cma_area; /* contiguous memory area for dma
943 allocations */
944 #endif
945 /* arch specific additions */
946 struct dev_archdata archdata;
947
948 struct device_node *of_node; /* associated device tree node */
949 struct fwnode_handle *fwnode; /* firmware device node */
950
951 dev_t devt; /* dev_t, creates the sysfs "dev" */
952 u32 id; /* device instance */
953
954 spinlock_t devres_lock;
955 struct list_head devres_head;
956
957 struct klist_node knode_class;
958 struct class *class;
959 const struct attribute_group **groups; /* optional groups */
960
961 void (*release)(struct device *dev);
962 struct iommu_group *iommu_group;
963 struct iommu_fwspec *iommu_fwspec;
964
965 bool offline_disabled:1;
966 bool offline:1;
967 bool of_node_reused:1;
968 };
969
970 static inline struct device *kobj_to_dev(struct kobject *kobj)
971 {
972 return container_of(kobj, struct device, kobj);
973 }
974
975 /* Get the wakeup routines, which depend on struct device */
976 #include <linux/pm_wakeup.h>
977
978 static inline const char *dev_name(const struct device *dev)
979 {
980 /* Use the init name until the kobject becomes available */
981 if (dev->init_name)
982 return dev->init_name;
983
984 return kobject_name(&dev->kobj);
985 }
986
987 extern __printf(2, 3)
988 int dev_set_name(struct device *dev, const char *name, ...);
989
990 #ifdef CONFIG_NUMA
991 static inline int dev_to_node(struct device *dev)
992 {
993 return dev->numa_node;
994 }
995 static inline void set_dev_node(struct device *dev, int node)
996 {
997 dev->numa_node = node;
998 }
999 #else
1000 static inline int dev_to_node(struct device *dev)
1001 {
1002 return -1;
1003 }
1004 static inline void set_dev_node(struct device *dev, int node)
1005 {
1006 }
1007 #endif
1008
1009 static inline struct irq_domain *dev_get_msi_domain(const struct device *dev)
1010 {
1011 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
1012 return dev->msi_domain;
1013 #else
1014 return NULL;
1015 #endif
1016 }
1017
1018 static inline void dev_set_msi_domain(struct device *dev, struct irq_domain *d)
1019 {
1020 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
1021 dev->msi_domain = d;
1022 #endif
1023 }
1024
1025 static inline void *dev_get_drvdata(const struct device *dev)
1026 {
1027 return dev->driver_data;
1028 }
1029
1030 static inline void dev_set_drvdata(struct device *dev, void *data)
1031 {
1032 dev->driver_data = data;
1033 }
1034
1035 static inline struct pm_subsys_data *dev_to_psd(struct device *dev)
1036 {
1037 return dev ? dev->power.subsys_data : NULL;
1038 }
1039
1040 static inline unsigned int dev_get_uevent_suppress(const struct device *dev)
1041 {
1042 return dev->kobj.uevent_suppress;
1043 }
1044
1045 static inline void dev_set_uevent_suppress(struct device *dev, int val)
1046 {
1047 dev->kobj.uevent_suppress = val;
1048 }
1049
1050 static inline int device_is_registered(struct device *dev)
1051 {
1052 return dev->kobj.state_in_sysfs;
1053 }
1054
1055 static inline void device_enable_async_suspend(struct device *dev)
1056 {
1057 if (!dev->power.is_prepared)
1058 dev->power.async_suspend = true;
1059 }
1060
1061 static inline void device_disable_async_suspend(struct device *dev)
1062 {
1063 if (!dev->power.is_prepared)
1064 dev->power.async_suspend = false;
1065 }
1066
1067 static inline bool device_async_suspend_enabled(struct device *dev)
1068 {
1069 return !!dev->power.async_suspend;
1070 }
1071
1072 static inline void dev_pm_syscore_device(struct device *dev, bool val)
1073 {
1074 #ifdef CONFIG_PM_SLEEP
1075 dev->power.syscore = val;
1076 #endif
1077 }
1078
1079 static inline void device_lock(struct device *dev)
1080 {
1081 mutex_lock(&dev->mutex);
1082 }
1083
1084 static inline int device_lock_interruptible(struct device *dev)
1085 {
1086 return mutex_lock_interruptible(&dev->mutex);
1087 }
1088
1089 static inline int device_trylock(struct device *dev)
1090 {
1091 return mutex_trylock(&dev->mutex);
1092 }
1093
1094 static inline void device_unlock(struct device *dev)
1095 {
1096 mutex_unlock(&dev->mutex);
1097 }
1098
1099 static inline void device_lock_assert(struct device *dev)
1100 {
1101 lockdep_assert_held(&dev->mutex);
1102 }
1103
1104 static inline struct device_node *dev_of_node(struct device *dev)
1105 {
1106 if (!IS_ENABLED(CONFIG_OF))
1107 return NULL;
1108 return dev->of_node;
1109 }
1110
1111 void driver_init(void);
1112
1113 /*
1114 * High level routines for use by the bus drivers
1115 */
1116 extern int __must_check device_register(struct device *dev);
1117 extern void device_unregister(struct device *dev);
1118 extern void device_initialize(struct device *dev);
1119 extern int __must_check device_add(struct device *dev);
1120 extern void device_del(struct device *dev);
1121 extern int device_for_each_child(struct device *dev, void *data,
1122 int (*fn)(struct device *dev, void *data));
1123 extern int device_for_each_child_reverse(struct device *dev, void *data,
1124 int (*fn)(struct device *dev, void *data));
1125 extern struct device *device_find_child(struct device *dev, void *data,
1126 int (*match)(struct device *dev, void *data));
1127 extern int device_rename(struct device *dev, const char *new_name);
1128 extern int device_move(struct device *dev, struct device *new_parent,
1129 enum dpm_order dpm_order);
1130 extern const char *device_get_devnode(struct device *dev,
1131 umode_t *mode, kuid_t *uid, kgid_t *gid,
1132 const char **tmp);
1133
1134 static inline bool device_supports_offline(struct device *dev)
1135 {
1136 return dev->bus && dev->bus->offline && dev->bus->online;
1137 }
1138
1139 extern void lock_device_hotplug(void);
1140 extern void unlock_device_hotplug(void);
1141 extern int lock_device_hotplug_sysfs(void);
1142 extern int device_offline(struct device *dev);
1143 extern int device_online(struct device *dev);
1144 extern void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode);
1145 extern void set_secondary_fwnode(struct device *dev, struct fwnode_handle *fwnode);
1146 void device_set_of_node_from_dev(struct device *dev, const struct device *dev2);
1147
1148 static inline int dev_num_vf(struct device *dev)
1149 {
1150 if (dev->bus && dev->bus->num_vf)
1151 return dev->bus->num_vf(dev);
1152 return 0;
1153 }
1154
1155 /*
1156 * Root device objects for grouping under /sys/devices
1157 */
1158 extern struct device *__root_device_register(const char *name,
1159 struct module *owner);
1160
1161 /* This is a macro to avoid include problems with THIS_MODULE */
1162 #define root_device_register(name) \
1163 __root_device_register(name, THIS_MODULE)
1164
1165 extern void root_device_unregister(struct device *root);
1166
1167 static inline void *dev_get_platdata(const struct device *dev)
1168 {
1169 return dev->platform_data;
1170 }
1171
1172 /*
1173 * Manual binding of a device to driver. See drivers/base/bus.c
1174 * for information on use.
1175 */
1176 extern int __must_check device_bind_driver(struct device *dev);
1177 extern void device_release_driver(struct device *dev);
1178 extern int __must_check device_attach(struct device *dev);
1179 extern int __must_check driver_attach(struct device_driver *drv);
1180 extern void device_initial_probe(struct device *dev);
1181 extern int __must_check device_reprobe(struct device *dev);
1182
1183 extern bool device_is_bound(struct device *dev);
1184
1185 /*
1186 * Easy functions for dynamically creating devices on the fly
1187 */
1188 extern __printf(5, 0)
1189 struct device *device_create_vargs(struct class *cls, struct device *parent,
1190 dev_t devt, void *drvdata,
1191 const char *fmt, va_list vargs);
1192 extern __printf(5, 6)
1193 struct device *device_create(struct class *cls, struct device *parent,
1194 dev_t devt, void *drvdata,
1195 const char *fmt, ...);
1196 extern __printf(6, 7)
1197 struct device *device_create_with_groups(struct class *cls,
1198 struct device *parent, dev_t devt, void *drvdata,
1199 const struct attribute_group **groups,
1200 const char *fmt, ...);
1201 extern void device_destroy(struct class *cls, dev_t devt);
1202
1203 /*
1204 * Platform "fixup" functions - allow the platform to have their say
1205 * about devices and actions that the general device layer doesn't
1206 * know about.
1207 */
1208 /* Notify platform of device discovery */
1209 extern int (*platform_notify)(struct device *dev);
1210
1211 extern int (*platform_notify_remove)(struct device *dev);
1212
1213
1214 /*
1215 * get_device - atomically increment the reference count for the device.
1216 *
1217 */
1218 extern struct device *get_device(struct device *dev);
1219 extern void put_device(struct device *dev);
1220
1221 #ifdef CONFIG_DEVTMPFS
1222 extern int devtmpfs_create_node(struct device *dev);
1223 extern int devtmpfs_delete_node(struct device *dev);
1224 extern int devtmpfs_mount(const char *mntdir);
1225 #else
1226 static inline int devtmpfs_create_node(struct device *dev) { return 0; }
1227 static inline int devtmpfs_delete_node(struct device *dev) { return 0; }
1228 static inline int devtmpfs_mount(const char *mountpoint) { return 0; }
1229 #endif
1230
1231 /* drivers/base/power/shutdown.c */
1232 extern void device_shutdown(void);
1233
1234 /* debugging and troubleshooting/diagnostic helpers. */
1235 extern const char *dev_driver_string(const struct device *dev);
1236
1237 /* Device links interface. */
1238 struct device_link *device_link_add(struct device *consumer,
1239 struct device *supplier, u32 flags);
1240 void device_link_del(struct device_link *link);
1241
1242 #ifdef CONFIG_PRINTK
1243
1244 extern __printf(3, 0)
1245 int dev_vprintk_emit(int level, const struct device *dev,
1246 const char *fmt, va_list args);
1247 extern __printf(3, 4)
1248 int dev_printk_emit(int level, const struct device *dev, const char *fmt, ...);
1249
1250 extern __printf(3, 4)
1251 void dev_printk(const char *level, const struct device *dev,
1252 const char *fmt, ...);
1253 extern __printf(2, 3)
1254 void dev_emerg(const struct device *dev, const char *fmt, ...);
1255 extern __printf(2, 3)
1256 void dev_alert(const struct device *dev, const char *fmt, ...);
1257 extern __printf(2, 3)
1258 void dev_crit(const struct device *dev, const char *fmt, ...);
1259 extern __printf(2, 3)
1260 void dev_err(const struct device *dev, const char *fmt, ...);
1261 extern __printf(2, 3)
1262 void dev_warn(const struct device *dev, const char *fmt, ...);
1263 extern __printf(2, 3)
1264 void dev_notice(const struct device *dev, const char *fmt, ...);
1265 extern __printf(2, 3)
1266 void _dev_info(const struct device *dev, const char *fmt, ...);
1267
1268 #else
1269
1270 static inline __printf(3, 0)
1271 int dev_vprintk_emit(int level, const struct device *dev,
1272 const char *fmt, va_list args)
1273 { return 0; }
1274 static inline __printf(3, 4)
1275 int dev_printk_emit(int level, const struct device *dev, const char *fmt, ...)
1276 { return 0; }
1277
1278 static inline void __dev_printk(const char *level, const struct device *dev,
1279 struct va_format *vaf)
1280 {}
1281 static inline __printf(3, 4)
1282 void dev_printk(const char *level, const struct device *dev,
1283 const char *fmt, ...)
1284 {}
1285
1286 static inline __printf(2, 3)
1287 void dev_emerg(const struct device *dev, const char *fmt, ...)
1288 {}
1289 static inline __printf(2, 3)
1290 void dev_crit(const struct device *dev, const char *fmt, ...)
1291 {}
1292 static inline __printf(2, 3)
1293 void dev_alert(const struct device *dev, const char *fmt, ...)
1294 {}
1295 static inline __printf(2, 3)
1296 void dev_err(const struct device *dev, const char *fmt, ...)
1297 {}
1298 static inline __printf(2, 3)
1299 void dev_warn(const struct device *dev, const char *fmt, ...)
1300 {}
1301 static inline __printf(2, 3)
1302 void dev_notice(const struct device *dev, const char *fmt, ...)
1303 {}
1304 static inline __printf(2, 3)
1305 void _dev_info(const struct device *dev, const char *fmt, ...)
1306 {}
1307
1308 #endif
1309
1310 /*
1311 * Stupid hackaround for existing uses of non-printk uses dev_info
1312 *
1313 * Note that the definition of dev_info below is actually _dev_info
1314 * and a macro is used to avoid redefining dev_info
1315 */
1316
1317 #define dev_info(dev, fmt, arg...) _dev_info(dev, fmt, ##arg)
1318
1319 #if defined(CONFIG_DYNAMIC_DEBUG)
1320 #define dev_dbg(dev, format, ...) \
1321 do { \
1322 dynamic_dev_dbg(dev, format, ##__VA_ARGS__); \
1323 } while (0)
1324 #elif defined(DEBUG)
1325 #define dev_dbg(dev, format, arg...) \
1326 dev_printk(KERN_DEBUG, dev, format, ##arg)
1327 #else
1328 #define dev_dbg(dev, format, arg...) \
1329 ({ \
1330 if (0) \
1331 dev_printk(KERN_DEBUG, dev, format, ##arg); \
1332 })
1333 #endif
1334
1335 #ifdef CONFIG_PRINTK
1336 #define dev_level_once(dev_level, dev, fmt, ...) \
1337 do { \
1338 static bool __print_once __read_mostly; \
1339 \
1340 if (!__print_once) { \
1341 __print_once = true; \
1342 dev_level(dev, fmt, ##__VA_ARGS__); \
1343 } \
1344 } while (0)
1345 #else
1346 #define dev_level_once(dev_level, dev, fmt, ...) \
1347 do { \
1348 if (0) \
1349 dev_level(dev, fmt, ##__VA_ARGS__); \
1350 } while (0)
1351 #endif
1352
1353 #define dev_emerg_once(dev, fmt, ...) \
1354 dev_level_once(dev_emerg, dev, fmt, ##__VA_ARGS__)
1355 #define dev_alert_once(dev, fmt, ...) \
1356 dev_level_once(dev_alert, dev, fmt, ##__VA_ARGS__)
1357 #define dev_crit_once(dev, fmt, ...) \
1358 dev_level_once(dev_crit, dev, fmt, ##__VA_ARGS__)
1359 #define dev_err_once(dev, fmt, ...) \
1360 dev_level_once(dev_err, dev, fmt, ##__VA_ARGS__)
1361 #define dev_warn_once(dev, fmt, ...) \
1362 dev_level_once(dev_warn, dev, fmt, ##__VA_ARGS__)
1363 #define dev_notice_once(dev, fmt, ...) \
1364 dev_level_once(dev_notice, dev, fmt, ##__VA_ARGS__)
1365 #define dev_info_once(dev, fmt, ...) \
1366 dev_level_once(dev_info, dev, fmt, ##__VA_ARGS__)
1367 #define dev_dbg_once(dev, fmt, ...) \
1368 dev_level_once(dev_dbg, dev, fmt, ##__VA_ARGS__)
1369
1370 #define dev_level_ratelimited(dev_level, dev, fmt, ...) \
1371 do { \
1372 static DEFINE_RATELIMIT_STATE(_rs, \
1373 DEFAULT_RATELIMIT_INTERVAL, \
1374 DEFAULT_RATELIMIT_BURST); \
1375 if (__ratelimit(&_rs)) \
1376 dev_level(dev, fmt, ##__VA_ARGS__); \
1377 } while (0)
1378
1379 #define dev_emerg_ratelimited(dev, fmt, ...) \
1380 dev_level_ratelimited(dev_emerg, dev, fmt, ##__VA_ARGS__)
1381 #define dev_alert_ratelimited(dev, fmt, ...) \
1382 dev_level_ratelimited(dev_alert, dev, fmt, ##__VA_ARGS__)
1383 #define dev_crit_ratelimited(dev, fmt, ...) \
1384 dev_level_ratelimited(dev_crit, dev, fmt, ##__VA_ARGS__)
1385 #define dev_err_ratelimited(dev, fmt, ...) \
1386 dev_level_ratelimited(dev_err, dev, fmt, ##__VA_ARGS__)
1387 #define dev_warn_ratelimited(dev, fmt, ...) \
1388 dev_level_ratelimited(dev_warn, dev, fmt, ##__VA_ARGS__)
1389 #define dev_notice_ratelimited(dev, fmt, ...) \
1390 dev_level_ratelimited(dev_notice, dev, fmt, ##__VA_ARGS__)
1391 #define dev_info_ratelimited(dev, fmt, ...) \
1392 dev_level_ratelimited(dev_info, dev, fmt, ##__VA_ARGS__)
1393 #if defined(CONFIG_DYNAMIC_DEBUG)
1394 /* descriptor check is first to prevent flooding with "callbacks suppressed" */
1395 #define dev_dbg_ratelimited(dev, fmt, ...) \
1396 do { \
1397 static DEFINE_RATELIMIT_STATE(_rs, \
1398 DEFAULT_RATELIMIT_INTERVAL, \
1399 DEFAULT_RATELIMIT_BURST); \
1400 DEFINE_DYNAMIC_DEBUG_METADATA(descriptor, fmt); \
1401 if (unlikely(descriptor.flags & _DPRINTK_FLAGS_PRINT) && \
1402 __ratelimit(&_rs)) \
1403 __dynamic_dev_dbg(&descriptor, dev, fmt, \
1404 ##__VA_ARGS__); \
1405 } while (0)
1406 #elif defined(DEBUG)
1407 #define dev_dbg_ratelimited(dev, fmt, ...) \
1408 do { \
1409 static DEFINE_RATELIMIT_STATE(_rs, \
1410 DEFAULT_RATELIMIT_INTERVAL, \
1411 DEFAULT_RATELIMIT_BURST); \
1412 if (__ratelimit(&_rs)) \
1413 dev_printk(KERN_DEBUG, dev, fmt, ##__VA_ARGS__); \
1414 } while (0)
1415 #else
1416 #define dev_dbg_ratelimited(dev, fmt, ...) \
1417 do { \
1418 if (0) \
1419 dev_printk(KERN_DEBUG, dev, fmt, ##__VA_ARGS__); \
1420 } while (0)
1421 #endif
1422
1423 #ifdef VERBOSE_DEBUG
1424 #define dev_vdbg dev_dbg
1425 #else
1426 #define dev_vdbg(dev, format, arg...) \
1427 ({ \
1428 if (0) \
1429 dev_printk(KERN_DEBUG, dev, format, ##arg); \
1430 })
1431 #endif
1432
1433 /*
1434 * dev_WARN*() acts like dev_printk(), but with the key difference of
1435 * using WARN/WARN_ONCE to include file/line information and a backtrace.
1436 */
1437 #define dev_WARN(dev, format, arg...) \
1438 WARN(1, "%s %s: " format, dev_driver_string(dev), dev_name(dev), ## arg);
1439
1440 #define dev_WARN_ONCE(dev, condition, format, arg...) \
1441 WARN_ONCE(condition, "%s %s: " format, \
1442 dev_driver_string(dev), dev_name(dev), ## arg)
1443
1444 /* Create alias, so I can be autoloaded. */
1445 #define MODULE_ALIAS_CHARDEV(major,minor) \
1446 MODULE_ALIAS("char-major-" __stringify(major) "-" __stringify(minor))
1447 #define MODULE_ALIAS_CHARDEV_MAJOR(major) \
1448 MODULE_ALIAS("char-major-" __stringify(major) "-*")
1449
1450 #ifdef CONFIG_SYSFS_DEPRECATED
1451 extern long sysfs_deprecated;
1452 #else
1453 #define sysfs_deprecated 0
1454 #endif
1455
1456 /**
1457 * module_driver() - Helper macro for drivers that don't do anything
1458 * special in module init/exit. This eliminates a lot of boilerplate.
1459 * Each module may only use this macro once, and calling it replaces
1460 * module_init() and module_exit().
1461 *
1462 * @__driver: driver name
1463 * @__register: register function for this driver type
1464 * @__unregister: unregister function for this driver type
1465 * @...: Additional arguments to be passed to __register and __unregister.
1466 *
1467 * Use this macro to construct bus specific macros for registering
1468 * drivers, and do not use it on its own.
1469 */
1470 #define module_driver(__driver, __register, __unregister, ...) \
1471 static int __init __driver##_init(void) \
1472 { \
1473 return __register(&(__driver) , ##__VA_ARGS__); \
1474 } \
1475 module_init(__driver##_init); \
1476 static void __exit __driver##_exit(void) \
1477 { \
1478 __unregister(&(__driver) , ##__VA_ARGS__); \
1479 } \
1480 module_exit(__driver##_exit);
1481
1482 /**
1483 * builtin_driver() - Helper macro for drivers that don't do anything
1484 * special in init and have no exit. This eliminates some boilerplate.
1485 * Each driver may only use this macro once, and calling it replaces
1486 * device_initcall (or in some cases, the legacy __initcall). This is
1487 * meant to be a direct parallel of module_driver() above but without
1488 * the __exit stuff that is not used for builtin cases.
1489 *
1490 * @__driver: driver name
1491 * @__register: register function for this driver type
1492 * @...: Additional arguments to be passed to __register
1493 *
1494 * Use this macro to construct bus specific macros for registering
1495 * drivers, and do not use it on its own.
1496 */
1497 #define builtin_driver(__driver, __register, ...) \
1498 static int __init __driver##_init(void) \
1499 { \
1500 return __register(&(__driver) , ##__VA_ARGS__); \
1501 } \
1502 device_initcall(__driver##_init);
1503
1504 #endif /* _DEVICE_H_ */ 1 /*
2 * kobject.h - generic kernel object infrastructure.
3 *
4 * Copyright (c) 2002-2003 Patrick Mochel
5 * Copyright (c) 2002-2003 Open Source Development Labs
6 * Copyright (c) 2006-2008 Greg Kroah-Hartman <greg@kroah.com>
7 * Copyright (c) 2006-2008 Novell Inc.
8 *
9 * This file is released under the GPLv2.
10 *
11 * Please read Documentation/kobject.txt before using the kobject
12 * interface, ESPECIALLY the parts about reference counts and object
13 * destructors.
14 */
15
16 #ifndef _KOBJECT_H_
17 #define _KOBJECT_H_
18
19 #include <linux/types.h>
20 #include <linux/list.h>
21 #include <linux/sysfs.h>
22 #include <linux/compiler.h>
23 #include <linux/spinlock.h>
24 #include <linux/kref.h>
25 #include <linux/kobject_ns.h>
26 #include <linux/kernel.h>
27 #include <linux/wait.h>
28 #include <linux/atomic.h>
29 #include <linux/workqueue.h>
30
31 #define UEVENT_HELPER_PATH_LEN 256
32 #define UEVENT_NUM_ENVP 32 /* number of env pointers */
33 #define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */
34
35 #ifdef CONFIG_UEVENT_HELPER
36 /* path to the userspace helper executed on an event */
37 extern char uevent_helper[];
38 #endif
39
40 /* counter to tag the uevent, read only except for the kobject core */
41 extern u64 uevent_seqnum;
42
43 /*
44 * The actions here must match the index to the string array
45 * in lib/kobject_uevent.c
46 *
47 * Do not add new actions here without checking with the driver-core
48 * maintainers. Action strings are not meant to express subsystem
49 * or device specific properties. In most cases you want to send a
50 * kobject_uevent_env(kobj, KOBJ_CHANGE, env) with additional event
51 * specific variables added to the event environment.
52 */
53 enum kobject_action {
54 KOBJ_ADD,
55 KOBJ_REMOVE,
56 KOBJ_CHANGE,
57 KOBJ_MOVE,
58 KOBJ_ONLINE,
59 KOBJ_OFFLINE,
60 KOBJ_MAX
61 };
62
63 struct kobject {
64 const char *name;
65 struct list_head entry;
66 struct kobject *parent;
67 struct kset *kset;
68 struct kobj_type *ktype;
69 struct kernfs_node *sd; /* sysfs directory entry */
70 struct kref kref;
71 #ifdef CONFIG_DEBUG_KOBJECT_RELEASE
72 struct delayed_work release;
73 #endif
74 unsigned int state_initialized:1;
75 unsigned int state_in_sysfs:1;
76 unsigned int state_add_uevent_sent:1;
77 unsigned int state_remove_uevent_sent:1;
78 unsigned int uevent_suppress:1;
79 };
80
81 extern __printf(2, 3)
82 int kobject_set_name(struct kobject *kobj, const char *name, ...);
83 extern __printf(2, 0)
84 int kobject_set_name_vargs(struct kobject *kobj, const char *fmt,
85 va_list vargs);
86
87 static inline const char *kobject_name(const struct kobject *kobj)
88 {
89 return kobj->name;
90 }
91
92 extern void kobject_init(struct kobject *kobj, struct kobj_type *ktype);
93 extern __printf(3, 4) __must_check
94 int kobject_add(struct kobject *kobj, struct kobject *parent,
95 const char *fmt, ...);
96 extern __printf(4, 5) __must_check
97 int kobject_init_and_add(struct kobject *kobj,
98 struct kobj_type *ktype, struct kobject *parent,
99 const char *fmt, ...);
100
101 extern void kobject_del(struct kobject *kobj);
102
103 extern struct kobject * __must_check kobject_create(void);
104 extern struct kobject * __must_check kobject_create_and_add(const char *name,
105 struct kobject *parent);
106
107 extern int __must_check kobject_rename(struct kobject *, const char *new_name);
108 extern int __must_check kobject_move(struct kobject *, struct kobject *);
109
110 extern struct kobject *kobject_get(struct kobject *kobj);
111 extern struct kobject * __must_check kobject_get_unless_zero(
112 struct kobject *kobj);
113 extern void kobject_put(struct kobject *kobj);
114
115 extern const void *kobject_namespace(struct kobject *kobj);
116 extern char *kobject_get_path(struct kobject *kobj, gfp_t flag);
117
118 struct kobj_type {
119 void (*release)(struct kobject *kobj);
120 const struct sysfs_ops *sysfs_ops;
121 struct attribute **default_attrs;
122 const struct kobj_ns_type_operations *(*child_ns_type)(struct kobject *kobj);
123 const void *(*namespace)(struct kobject *kobj);
124 };
125
126 struct kobj_uevent_env {
127 char *argv[3];
128 char *envp[UEVENT_NUM_ENVP];
129 int envp_idx;
130 char buf[UEVENT_BUFFER_SIZE];
131 int buflen;
132 };
133
134 struct kset_uevent_ops {
135 int (* const filter)(struct kset *kset, struct kobject *kobj);
136 const char *(* const name)(struct kset *kset, struct kobject *kobj);
137 int (* const uevent)(struct kset *kset, struct kobject *kobj,
138 struct kobj_uevent_env *env);
139 };
140
141 struct kobj_attribute {
142 struct attribute attr;
143 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
144 char *buf);
145 ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
146 const char *buf, size_t count);
147 };
148
149 extern const struct sysfs_ops kobj_sysfs_ops;
150
151 struct sock;
152
153 /**
154 * struct kset - a set of kobjects of a specific type, belonging to a specific subsystem.
155 *
156 * A kset defines a group of kobjects. They can be individually
157 * different "types" but overall these kobjects all want to be grouped
158 * together and operated on in the same manner. ksets are used to
159 * define the attribute callbacks and other common events that happen to
160 * a kobject.
161 *
162 * @list: the list of all kobjects for this kset
163 * @list_lock: a lock for iterating over the kobjects
164 * @kobj: the embedded kobject for this kset (recursion, isn't it fun...)
165 * @uevent_ops: the set of uevent operations for this kset. These are
166 * called whenever a kobject has something happen to it so that the kset
167 * can add new environment variables, or filter out the uevents if so
168 * desired.
169 */
170 struct kset {
171 struct list_head list;
172 spinlock_t list_lock;
173 struct kobject kobj;
174 const struct kset_uevent_ops *uevent_ops;
175 };
176
177 extern void kset_init(struct kset *kset);
178 extern int __must_check kset_register(struct kset *kset);
179 extern void kset_unregister(struct kset *kset);
180 extern struct kset * __must_check kset_create_and_add(const char *name,
181 const struct kset_uevent_ops *u,
182 struct kobject *parent_kobj);
183
184 static inline struct kset *to_kset(struct kobject *kobj)
185 {
186 return kobj ? container_of(kobj, struct kset, kobj) : NULL;
187 }
188
189 static inline struct kset *kset_get(struct kset *k)
190 {
191 return k ? to_kset(kobject_get(&k->kobj)) : NULL;
192 }
193
194 static inline void kset_put(struct kset *k)
195 {
196 kobject_put(&k->kobj);
197 }
198
199 static inline struct kobj_type *get_ktype(struct kobject *kobj)
200 {
201 return kobj->ktype;
202 }
203
204 extern struct kobject *kset_find_obj(struct kset *, const char *);
205
206 /* The global /sys/kernel/ kobject for people to chain off of */
207 extern struct kobject *kernel_kobj;
208 /* The global /sys/kernel/mm/ kobject for people to chain off of */
209 extern struct kobject *mm_kobj;
210 /* The global /sys/hypervisor/ kobject for people to chain off of */
211 extern struct kobject *hypervisor_kobj;
212 /* The global /sys/power/ kobject for people to chain off of */
213 extern struct kobject *power_kobj;
214 /* The global /sys/firmware/ kobject for people to chain off of */
215 extern struct kobject *firmware_kobj;
216
217 int kobject_uevent(struct kobject *kobj, enum kobject_action action);
218 int kobject_uevent_env(struct kobject *kobj, enum kobject_action action,
219 char *envp[]);
220 int kobject_synth_uevent(struct kobject *kobj, const char *buf, size_t count);
221
222 __printf(2, 3)
223 int add_uevent_var(struct kobj_uevent_env *env, const char *format, ...);
224
225 #endif /* _KOBJECT_H_ */ 1 /*
2 * platform_device.h - generic, centralized driver model
3 *
4 * Copyright (c) 2001-2003 Patrick Mochel <mochel@osdl.org>
5 *
6 * This file is released under the GPLv2
7 *
8 * See Documentation/driver-model/ for more information.
9 */
10
11 #ifndef _PLATFORM_DEVICE_H_
12 #define _PLATFORM_DEVICE_H_
13
14 #include <linux/device.h>
15 #include <linux/mod_devicetable.h>
16
17 #define PLATFORM_DEVID_NONE (-1)
18 #define PLATFORM_DEVID_AUTO (-2)
19
20 struct mfd_cell;
21 struct property_entry;
22
23 struct platform_device {
24 const char *name;
25 int id;
26 bool id_auto;
27 struct device dev;
28 u32 num_resources;
29 struct resource *resource;
30
31 const struct platform_device_id *id_entry;
32 char *driver_override; /* Driver name to force a match */
33
34 /* MFD cell pointer */
35 struct mfd_cell *mfd_cell;
36
37 /* arch specific additions */
38 struct pdev_archdata archdata;
39 };
40
41 #define platform_get_device_id(pdev) ((pdev)->id_entry)
42
43 #define to_platform_device(x) container_of((x), struct platform_device, dev)
44
45 extern int platform_device_register(struct platform_device *);
46 extern void platform_device_unregister(struct platform_device *);
47
48 extern struct bus_type platform_bus_type;
49 extern struct device platform_bus;
50
51 extern void arch_setup_pdev_archdata(struct platform_device *);
52 extern struct resource *platform_get_resource(struct platform_device *,
53 unsigned int, unsigned int);
54 extern int platform_get_irq(struct platform_device *, unsigned int);
55 extern int platform_irq_count(struct platform_device *);
56 extern struct resource *platform_get_resource_byname(struct platform_device *,
57 unsigned int,
58 const char *);
59 extern int platform_get_irq_byname(struct platform_device *, const char *);
60 extern int platform_add_devices(struct platform_device **, int);
61
62 struct platform_device_info {
63 struct device *parent;
64 struct fwnode_handle *fwnode;
65
66 const char *name;
67 int id;
68
69 const struct resource *res;
70 unsigned int num_res;
71
72 const void *data;
73 size_t size_data;
74 u64 dma_mask;
75
76 struct property_entry *properties;
77 };
78 extern struct platform_device *platform_device_register_full(
79 const struct platform_device_info *pdevinfo);
80
81 /**
82 * platform_device_register_resndata - add a platform-level device with
83 * resources and platform-specific data
84 *
85 * @parent: parent device for the device we're adding
86 * @name: base name of the device we're adding
87 * @id: instance id
88 * @res: set of resources that needs to be allocated for the device
89 * @num: number of resources
90 * @data: platform specific data for this platform device
91 * @size: size of platform specific data
92 *
93 * Returns &struct platform_device pointer on success, or ERR_PTR() on error.
94 */
95 static inline struct platform_device *platform_device_register_resndata(
96 struct device *parent, const char *name, int id,
97 const struct resource *res, unsigned int num,
98 const void *data, size_t size) {
99
100 struct platform_device_info pdevinfo = {
101 .parent = parent,
102 .name = name,
103 .id = id,
104 .res = res,
105 .num_res = num,
106 .data = data,
107 .size_data = size,
108 .dma_mask = 0,
109 };
110
111 return platform_device_register_full(&pdevinfo);
112 }
113
114 /**
115 * platform_device_register_simple - add a platform-level device and its resources
116 * @name: base name of the device we're adding
117 * @id: instance id
118 * @res: set of resources that needs to be allocated for the device
119 * @num: number of resources
120 *
121 * This function creates a simple platform device that requires minimal
122 * resource and memory management. Canned release function freeing memory
123 * allocated for the device allows drivers using such devices to be
124 * unloaded without waiting for the last reference to the device to be
125 * dropped.
126 *
127 * This interface is primarily intended for use with legacy drivers which
128 * probe hardware directly. Because such drivers create sysfs device nodes
129 * themselves, rather than letting system infrastructure handle such device
130 * enumeration tasks, they don't fully conform to the Linux driver model.
131 * In particular, when such drivers are built as modules, they can't be
132 * "hotplugged".
133 *
134 * Returns &struct platform_device pointer on success, or ERR_PTR() on error.
135 */
136 static inline struct platform_device *platform_device_register_simple(
137 const char *name, int id,
138 const struct resource *res, unsigned int num)
139 {
140 return platform_device_register_resndata(NULL, name, id,
141 res, num, NULL, 0);
142 }
143
144 /**
145 * platform_device_register_data - add a platform-level device with platform-specific data
146 * @parent: parent device for the device we're adding
147 * @name: base name of the device we're adding
148 * @id: instance id
149 * @data: platform specific data for this platform device
150 * @size: size of platform specific data
151 *
152 * This function creates a simple platform device that requires minimal
153 * resource and memory management. Canned release function freeing memory
154 * allocated for the device allows drivers using such devices to be
155 * unloaded without waiting for the last reference to the device to be
156 * dropped.
157 *
158 * Returns &struct platform_device pointer on success, or ERR_PTR() on error.
159 */
160 static inline struct platform_device *platform_device_register_data(
161 struct device *parent, const char *name, int id,
162 const void *data, size_t size)
163 {
164 return platform_device_register_resndata(parent, name, id,
165 NULL, 0, data, size);
166 }
167
168 extern struct platform_device *platform_device_alloc(const char *name, int id);
169 extern int platform_device_add_resources(struct platform_device *pdev,
170 const struct resource *res,
171 unsigned int num);
172 extern int platform_device_add_data(struct platform_device *pdev,
173 const void *data, size_t size);
174 extern int platform_device_add_properties(struct platform_device *pdev,
175 const struct property_entry *properties);
176 extern int platform_device_add(struct platform_device *pdev);
177 extern void platform_device_del(struct platform_device *pdev);
178 extern void platform_device_put(struct platform_device *pdev);
179
180 struct platform_driver {
181 int (*probe)(struct platform_device *);
182 int (*remove)(struct platform_device *);
183 void (*shutdown)(struct platform_device *);
184 int (*suspend)(struct platform_device *, pm_message_t state);
185 int (*resume)(struct platform_device *);
186 struct device_driver driver;
187 const struct platform_device_id *id_table;
188 bool prevent_deferred_probe;
189 };
190
191 #define to_platform_driver(drv) (container_of((drv), struct platform_driver, \
192 driver))
193
194 /*
195 * use a macro to avoid include chaining to get THIS_MODULE
196 */
197 #define platform_driver_register(drv) \
198 __platform_driver_register(drv, THIS_MODULE)
199 extern int __platform_driver_register(struct platform_driver *,
200 struct module *);
201 extern void platform_driver_unregister(struct platform_driver *);
202
203 /* non-hotpluggable platform devices may use this so that probe() and
204 * its support may live in __init sections, conserving runtime memory.
205 */
206 #define platform_driver_probe(drv, probe) \
207 __platform_driver_probe(drv, probe, THIS_MODULE)
208 extern int __platform_driver_probe(struct platform_driver *driver,
209 int (*probe)(struct platform_device *), struct module *module);
210
211 static inline void *platform_get_drvdata(const struct platform_device *pdev)
212 {
213 return dev_get_drvdata(&pdev->dev);
214 }
215
216 static inline void platform_set_drvdata(struct platform_device *pdev,
217 void *data)
218 {
219 dev_set_drvdata(&pdev->dev, data);
220 }
221
222 /* module_platform_driver() - Helper macro for drivers that don't do
223 * anything special in module init/exit. This eliminates a lot of
224 * boilerplate. Each module may only use this macro once, and
225 * calling it replaces module_init() and module_exit()
226 */
227 #define module_platform_driver(__platform_driver) \
228 module_driver(__platform_driver, platform_driver_register, \
229 platform_driver_unregister)
230
231 /* builtin_platform_driver() - Helper macro for builtin drivers that
232 * don't do anything special in driver init. This eliminates some
233 * boilerplate. Each driver may only use this macro once, and
234 * calling it replaces device_initcall(). Note this is meant to be
235 * a parallel of module_platform_driver() above, but w/o _exit stuff.
236 */
237 #define builtin_platform_driver(__platform_driver) \
238 builtin_driver(__platform_driver, platform_driver_register)
239
240 /* module_platform_driver_probe() - Helper macro for drivers that don't do
241 * anything special in module init/exit. This eliminates a lot of
242 * boilerplate. Each module may only use this macro once, and
243 * calling it replaces module_init() and module_exit()
244 */
245 #define module_platform_driver_probe(__platform_driver, __platform_probe) \
246 static int __init __platform_driver##_init(void) \
247 { \
248 return platform_driver_probe(&(__platform_driver), \
249 __platform_probe); \
250 } \
251 module_init(__platform_driver##_init); \
252 static void __exit __platform_driver##_exit(void) \
253 { \
254 platform_driver_unregister(&(__platform_driver)); \
255 } \
256 module_exit(__platform_driver##_exit);
257
258 /* builtin_platform_driver_probe() - Helper macro for drivers that don't do
259 * anything special in device init. This eliminates some boilerplate. Each
260 * driver may only use this macro once, and using it replaces device_initcall.
261 * This is meant to be a parallel of module_platform_driver_probe above, but
262 * without the __exit parts.
263 */
264 #define builtin_platform_driver_probe(__platform_driver, __platform_probe) \
265 static int __init __platform_driver##_init(void) \
266 { \
267 return platform_driver_probe(&(__platform_driver), \
268 __platform_probe); \
269 } \
270 device_initcall(__platform_driver##_init); \
271
272 #define platform_create_bundle(driver, probe, res, n_res, data, size) \
273 __platform_create_bundle(driver, probe, res, n_res, data, size, THIS_MODULE)
274 extern struct platform_device *__platform_create_bundle(
275 struct platform_driver *driver, int (*probe)(struct platform_device *),
276 struct resource *res, unsigned int n_res,
277 const void *data, size_t size, struct module *module);
278
279 int __platform_register_drivers(struct platform_driver * const *drivers,
280 unsigned int count, struct module *owner);
281 void platform_unregister_drivers(struct platform_driver * const *drivers,
282 unsigned int count);
283
284 #define platform_register_drivers(drivers, count) \
285 __platform_register_drivers(drivers, count, THIS_MODULE)
286
287 /* early platform driver interface */
288 struct early_platform_driver {
289 const char *class_str;
290 struct platform_driver *pdrv;
291 struct list_head list;
292 int requested_id;
293 char *buffer;
294 int bufsize;
295 };
296
297 #define EARLY_PLATFORM_ID_UNSET -2
298 #define EARLY_PLATFORM_ID_ERROR -3
299
300 extern int early_platform_driver_register(struct early_platform_driver *epdrv,
301 char *buf);
302 extern void early_platform_add_devices(struct platform_device **devs, int num);
303
304 static inline int is_early_platform_device(struct platform_device *pdev)
305 {
306 return !pdev->dev.driver;
307 }
308
309 extern void early_platform_driver_register_all(char *class_str);
310 extern int early_platform_driver_probe(char *class_str,
311 int nr_probe, int user_only);
312 extern void early_platform_cleanup(void);
313
314 #define early_platform_init(class_string, platdrv) \
315 early_platform_init_buffer(class_string, platdrv, NULL, 0)
316
317 #ifndef MODULE
318 #define early_platform_init_buffer(class_string, platdrv, buf, bufsiz) \
319 static __initdata struct early_platform_driver early_driver = { \
320 .class_str = class_string, \
321 .buffer = buf, \
322 .bufsize = bufsiz, \
323 .pdrv = platdrv, \
324 .requested_id = EARLY_PLATFORM_ID_UNSET, \
325 }; \
326 static int __init early_platform_driver_setup_func(char *buffer) \
327 { \
328 return early_platform_driver_register(&early_driver, buffer); \
329 } \
330 early_param(class_string, early_platform_driver_setup_func)
331 #else /* MODULE */
332 #define early_platform_init_buffer(class_string, platdrv, buf, bufsiz) \
333 static inline char *early_platform_driver_setup_func(void) \
334 { \
335 return bufsiz ? buf : NULL; \
336 }
337 #endif /* MODULE */
338
339 #ifdef CONFIG_SUSPEND
340 extern int platform_pm_suspend(struct device *dev);
341 extern int platform_pm_resume(struct device *dev);
342 #else
343 #define platform_pm_suspend NULL
344 #define platform_pm_resume NULL
345 #endif
346
347 #ifdef CONFIG_HIBERNATE_CALLBACKS
348 extern int platform_pm_freeze(struct device *dev);
349 extern int platform_pm_thaw(struct device *dev);
350 extern int platform_pm_poweroff(struct device *dev);
351 extern int platform_pm_restore(struct device *dev);
352 #else
353 #define platform_pm_freeze NULL
354 #define platform_pm_thaw NULL
355 #define platform_pm_poweroff NULL
356 #define platform_pm_restore NULL
357 #endif
358
359 #ifdef CONFIG_PM_SLEEP
360 #define USE_PLATFORM_PM_SLEEP_OPS \
361 .suspend = platform_pm_suspend, \
362 .resume = platform_pm_resume, \
363 .freeze = platform_pm_freeze, \
364 .thaw = platform_pm_thaw, \
365 .poweroff = platform_pm_poweroff, \
366 .restore = platform_pm_restore,
367 #else
368 #define USE_PLATFORM_PM_SLEEP_OPS
369 #endif
370
371 #endif /* _PLATFORM_DEVICE_H_ */ 1 #ifndef __LINUX_SPINLOCK_H
2 #define __LINUX_SPINLOCK_H
3
4 /*
5 * include/linux/spinlock.h - generic spinlock/rwlock declarations
6 *
7 * here's the role of the various spinlock/rwlock related include files:
8 *
9 * on SMP builds:
10 *
11 * asm/spinlock_types.h: contains the arch_spinlock_t/arch_rwlock_t and the
12 * initializers
13 *
14 * linux/spinlock_types.h:
15 * defines the generic type and initializers
16 *
17 * asm/spinlock.h: contains the arch_spin_*()/etc. lowlevel
18 * implementations, mostly inline assembly code
19 *
20 * (also included on UP-debug builds:)
21 *
22 * linux/spinlock_api_smp.h:
23 * contains the prototypes for the _spin_*() APIs.
24 *
25 * linux/spinlock.h: builds the final spin_*() APIs.
26 *
27 * on UP builds:
28 *
29 * linux/spinlock_type_up.h:
30 * contains the generic, simplified UP spinlock type.
31 * (which is an empty structure on non-debug builds)
32 *
33 * linux/spinlock_types.h:
34 * defines the generic type and initializers
35 *
36 * linux/spinlock_up.h:
37 * contains the arch_spin_*()/etc. version of UP
38 * builds. (which are NOPs on non-debug, non-preempt
39 * builds)
40 *
41 * (included on UP-non-debug builds:)
42 *
43 * linux/spinlock_api_up.h:
44 * builds the _spin_*() APIs.
45 *
46 * linux/spinlock.h: builds the final spin_*() APIs.
47 */
48
49 #include <linux/typecheck.h>
50 #include <linux/preempt.h>
51 #include <linux/linkage.h>
52 #include <linux/compiler.h>
53 #include <linux/irqflags.h>
54 #include <linux/thread_info.h>
55 #include <linux/kernel.h>
56 #include <linux/stringify.h>
57 #include <linux/bottom_half.h>
58 #include <asm/barrier.h>
59
60
61 /*
62 * Must define these before including other files, inline functions need them
63 */
64 #define LOCK_SECTION_NAME ".text..lock."KBUILD_BASENAME
65
66 #define LOCK_SECTION_START(extra) \
67 ".subsection 1\n\t" \
68 extra \
69 ".ifndef " LOCK_SECTION_NAME "\n\t" \
70 LOCK_SECTION_NAME ":\n\t" \
71 ".endif\n"
72
73 #define LOCK_SECTION_END \
74 ".previous\n\t"
75
76 #define __lockfunc __attribute__((section(".spinlock.text")))
77
78 /*
79 * Pull the arch_spinlock_t and arch_rwlock_t definitions:
80 */
81 #include <linux/spinlock_types.h>
82
83 /*
84 * Pull the arch_spin*() functions/declarations (UP-nondebug doesn't need them):
85 */
86 #ifdef CONFIG_SMP
87 # include <asm/spinlock.h>
88 #else
89 # include <linux/spinlock_up.h>
90 #endif
91
92 #ifdef CONFIG_DEBUG_SPINLOCK
93 extern void __raw_spin_lock_init(raw_spinlock_t *lock, const char *name,
94 struct lock_class_key *key);
95 # define raw_spin_lock_init(lock) \
96 do { \
97 static struct lock_class_key __key; \
98 \
99 __raw_spin_lock_init((lock), #lock, &__key); \
100 } while (0)
101
102 #else
103 # define raw_spin_lock_init(lock) \
104 do { *(lock) = __RAW_SPIN_LOCK_UNLOCKED(lock); } while (0)
105 #endif
106
107 #define raw_spin_is_locked(lock) arch_spin_is_locked(&(lock)->raw_lock)
108
109 #ifdef CONFIG_GENERIC_LOCKBREAK
110 #define raw_spin_is_contended(lock) ((lock)->break_lock)
111 #else
112
113 #ifdef arch_spin_is_contended
114 #define raw_spin_is_contended(lock) arch_spin_is_contended(&(lock)->raw_lock)
115 #else
116 #define raw_spin_is_contended(lock) (((void)(lock), 0))
117 #endif /*arch_spin_is_contended*/
118 #endif
119
120 /*
121 * Despite its name it doesn't necessarily has to be a full barrier.
122 * It should only guarantee that a STORE before the critical section
123 * can not be reordered with LOADs and STOREs inside this section.
124 * spin_lock() is the one-way barrier, this LOAD can not escape out
125 * of the region. So the default implementation simply ensures that
126 * a STORE can not move into the critical section, smp_wmb() should
127 * serialize it with another STORE done by spin_lock().
128 */
129 #ifndef smp_mb__before_spinlock
130 #define smp_mb__before_spinlock() smp_wmb()
131 #endif
132
133 /**
134 * raw_spin_unlock_wait - wait until the spinlock gets unlocked
135 * @lock: the spinlock in question.
136 */
137 #define raw_spin_unlock_wait(lock) arch_spin_unlock_wait(&(lock)->raw_lock)
138
139 #ifdef CONFIG_DEBUG_SPINLOCK
140 extern void do_raw_spin_lock(raw_spinlock_t *lock) __acquires(lock);
141 #define do_raw_spin_lock_flags(lock, flags) do_raw_spin_lock(lock)
142 extern int do_raw_spin_trylock(raw_spinlock_t *lock);
143 extern void do_raw_spin_unlock(raw_spinlock_t *lock) __releases(lock);
144 #else
145 static inline void do_raw_spin_lock(raw_spinlock_t *lock) __acquires(lock)
146 {
147 __acquire(lock);
148 arch_spin_lock(&lock->raw_lock);
149 }
150
151 static inline void
152 do_raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long *flags) __acquires(lock)
153 {
154 __acquire(lock);
155 arch_spin_lock_flags(&lock->raw_lock, *flags);
156 }
157
158 static inline int do_raw_spin_trylock(raw_spinlock_t *lock)
159 {
160 return arch_spin_trylock(&(lock)->raw_lock);
161 }
162
163 static inline void do_raw_spin_unlock(raw_spinlock_t *lock) __releases(lock)
164 {
165 arch_spin_unlock(&lock->raw_lock);
166 __release(lock);
167 }
168 #endif
169
170 /*
171 * Define the various spin_lock methods. Note we define these
172 * regardless of whether CONFIG_SMP or CONFIG_PREEMPT are set. The
173 * various methods are defined as nops in the case they are not
174 * required.
175 */
176 #define raw_spin_trylock(lock) __cond_lock(lock, _raw_spin_trylock(lock))
177
178 #define raw_spin_lock(lock) _raw_spin_lock(lock)
179
180 #ifdef CONFIG_DEBUG_LOCK_ALLOC
181 # define raw_spin_lock_nested(lock, subclass) \
182 _raw_spin_lock_nested(lock, subclass)
183
184 # define raw_spin_lock_nest_lock(lock, nest_lock) \
185 do { \
186 typecheck(struct lockdep_map *, &(nest_lock)->dep_map);\
187 _raw_spin_lock_nest_lock(lock, &(nest_lock)->dep_map); \
188 } while (0)
189 #else
190 /*
191 * Always evaluate the 'subclass' argument to avoid that the compiler
192 * warns about set-but-not-used variables when building with
193 * CONFIG_DEBUG_LOCK_ALLOC=n and with W=1.
194 */
195 # define raw_spin_lock_nested(lock, subclass) \
196 _raw_spin_lock(((void)(subclass), (lock)))
197 # define raw_spin_lock_nest_lock(lock, nest_lock) _raw_spin_lock(lock)
198 #endif
199
200 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_SPINLOCK)
201
202 #define raw_spin_lock_irqsave(lock, flags) \
203 do { \
204 typecheck(unsigned long, flags); \
205 flags = _raw_spin_lock_irqsave(lock); \
206 } while (0)
207
208 #ifdef CONFIG_DEBUG_LOCK_ALLOC
209 #define raw_spin_lock_irqsave_nested(lock, flags, subclass) \
210 do { \
211 typecheck(unsigned long, flags); \
212 flags = _raw_spin_lock_irqsave_nested(lock, subclass); \
213 } while (0)
214 #else
215 #define raw_spin_lock_irqsave_nested(lock, flags, subclass) \
216 do { \
217 typecheck(unsigned long, flags); \
218 flags = _raw_spin_lock_irqsave(lock); \
219 } while (0)
220 #endif
221
222 #else
223
224 #define raw_spin_lock_irqsave(lock, flags) \
225 do { \
226 typecheck(unsigned long, flags); \
227 _raw_spin_lock_irqsave(lock, flags); \
228 } while (0)
229
230 #define raw_spin_lock_irqsave_nested(lock, flags, subclass) \
231 raw_spin_lock_irqsave(lock, flags)
232
233 #endif
234
235 #define raw_spin_lock_irq(lock) _raw_spin_lock_irq(lock)
236 #define raw_spin_lock_bh(lock) _raw_spin_lock_bh(lock)
237 #define raw_spin_unlock(lock) _raw_spin_unlock(lock)
238 #define raw_spin_unlock_irq(lock) _raw_spin_unlock_irq(lock)
239
240 #define raw_spin_unlock_irqrestore(lock, flags) \
241 do { \
242 typecheck(unsigned long, flags); \
243 _raw_spin_unlock_irqrestore(lock, flags); \
244 } while (0)
245 #define raw_spin_unlock_bh(lock) _raw_spin_unlock_bh(lock)
246
247 #define raw_spin_trylock_bh(lock) \
248 __cond_lock(lock, _raw_spin_trylock_bh(lock))
249
250 #define raw_spin_trylock_irq(lock) \
251 ({ \
252 local_irq_disable(); \
253 raw_spin_trylock(lock) ? \
254 1 : ({ local_irq_enable(); 0; }); \
255 })
256
257 #define raw_spin_trylock_irqsave(lock, flags) \
258 ({ \
259 local_irq_save(flags); \
260 raw_spin_trylock(lock) ? \
261 1 : ({ local_irq_restore(flags); 0; }); \
262 })
263
264 /**
265 * raw_spin_can_lock - would raw_spin_trylock() succeed?
266 * @lock: the spinlock in question.
267 */
268 #define raw_spin_can_lock(lock) (!raw_spin_is_locked(lock))
269
270 /* Include rwlock functions */
271 #include <linux/rwlock.h>
272
273 /*
274 * Pull the _spin_*()/_read_*()/_write_*() functions/declarations:
275 */
276 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_SPINLOCK)
277 # include <linux/spinlock_api_smp.h>
278 #else
279 # include <linux/spinlock_api_up.h>
280 #endif
281
282 /*
283 * Map the spin_lock functions to the raw variants for PREEMPT_RT=n
284 */
285
286 static __always_inline raw_spinlock_t *spinlock_check(spinlock_t *lock)
287 {
288 return &lock->rlock;
289 }
290
291 #define spin_lock_init(_lock) \
292 do { \
293 spinlock_check(_lock); \
294 raw_spin_lock_init(&(_lock)->rlock); \
295 } while (0)
296
297 static __always_inline void spin_lock(spinlock_t *lock)
298 {
299 raw_spin_lock(&lock->rlock);
300 }
301
302 static __always_inline void spin_lock_bh(spinlock_t *lock)
303 {
304 raw_spin_lock_bh(&lock->rlock);
305 }
306
307 static __always_inline int spin_trylock(spinlock_t *lock)
308 {
309 return raw_spin_trylock(&lock->rlock);
310 }
311
312 #define spin_lock_nested(lock, subclass) \
313 do { \
314 raw_spin_lock_nested(spinlock_check(lock), subclass); \
315 } while (0)
316
317 #define spin_lock_nest_lock(lock, nest_lock) \
318 do { \
319 raw_spin_lock_nest_lock(spinlock_check(lock), nest_lock); \
320 } while (0)
321
322 static __always_inline void spin_lock_irq(spinlock_t *lock)
323 {
324 raw_spin_lock_irq(&lock->rlock);
325 }
326
327 #define spin_lock_irqsave(lock, flags) \
328 do { \
329 raw_spin_lock_irqsave(spinlock_check(lock), flags); \
330 } while (0)
331
332 #define spin_lock_irqsave_nested(lock, flags, subclass) \
333 do { \
334 raw_spin_lock_irqsave_nested(spinlock_check(lock), flags, subclass); \
335 } while (0)
336
337 static __always_inline void spin_unlock(spinlock_t *lock)
338 {
339 raw_spin_unlock(&lock->rlock);
340 }
341
342 static __always_inline void spin_unlock_bh(spinlock_t *lock)
343 {
344 raw_spin_unlock_bh(&lock->rlock);
345 }
346
347 static __always_inline void spin_unlock_irq(spinlock_t *lock)
348 {
349 raw_spin_unlock_irq(&lock->rlock);
350 }
351
352 static __always_inline void spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags)
353 {
354 raw_spin_unlock_irqrestore(&lock->rlock, flags);
355 }
356
357 static __always_inline int spin_trylock_bh(spinlock_t *lock)
358 {
359 return raw_spin_trylock_bh(&lock->rlock);
360 }
361
362 static __always_inline int spin_trylock_irq(spinlock_t *lock)
363 {
364 return raw_spin_trylock_irq(&lock->rlock);
365 }
366
367 #define spin_trylock_irqsave(lock, flags) \
368 ({ \
369 raw_spin_trylock_irqsave(spinlock_check(lock), flags); \
370 })
371
372 /**
373 * spin_unlock_wait - Interpose between successive critical sections
374 * @lock: the spinlock whose critical sections are to be interposed.
375 *
376 * Semantically this is equivalent to a spin_lock() immediately
377 * followed by a spin_unlock(). However, most architectures have
378 * more efficient implementations in which the spin_unlock_wait()
379 * cannot block concurrent lock acquisition, and in some cases
380 * where spin_unlock_wait() does not write to the lock variable.
381 * Nevertheless, spin_unlock_wait() can have high overhead, so if
382 * you feel the need to use it, please check to see if there is
383 * a better way to get your job done.
384 *
385 * The ordering guarantees provided by spin_unlock_wait() are:
386 *
387 * 1. All accesses preceding the spin_unlock_wait() happen before
388 * any accesses in later critical sections for this same lock.
389 * 2. All accesses following the spin_unlock_wait() happen after
390 * any accesses in earlier critical sections for this same lock.
391 */
392 static __always_inline void spin_unlock_wait(spinlock_t *lock)
393 {
394 raw_spin_unlock_wait(&lock->rlock);
395 }
396
397 static __always_inline int spin_is_locked(spinlock_t *lock)
398 {
399 return raw_spin_is_locked(&lock->rlock);
400 }
401
402 static __always_inline int spin_is_contended(spinlock_t *lock)
403 {
404 return raw_spin_is_contended(&lock->rlock);
405 }
406
407 static __always_inline int spin_can_lock(spinlock_t *lock)
408 {
409 return raw_spin_can_lock(&lock->rlock);
410 }
411
412 #define assert_spin_locked(lock) assert_raw_spin_locked(&(lock)->rlock)
413
414 /*
415 * Pull the atomic_t declaration:
416 * (asm-mips/atomic.h needs above definitions)
417 */
418 #include <linux/atomic.h>
419 /**
420 * atomic_dec_and_lock - lock on reaching reference count zero
421 * @atomic: the atomic counter
422 * @lock: the spinlock in question
423 *
424 * Decrements @atomic by 1. If the result is 0, returns true and locks
425 * @lock. Returns false for all other cases.
426 */
427 extern int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock);
428 #define atomic_dec_and_lock(atomic, lock) \
429 __cond_lock(lock, _atomic_dec_and_lock(atomic, lock))
430
431 #endif /* __LINUX_SPINLOCK_H */ |
Here is an explanation of a rule violation arisen while checking your driver against a corresponding kernel.
Note that it may be false positive, i.e. there isn't a real error indeed. Please analyze a given error trace and related source code to understand whether there is an error in your driver.
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| Ядро | Модуль | Правило | Верификатор | Вердикт | Статус | Время создания | Описание проблемы |
| linux-4.13-rc1 | drivers/tty/serial/sccnxp.ko | 320_7a | CPAchecker | Bug | Fixed | 2017-09-02 23:15:32 | L0295 |
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Reported: 2 Sep 2017
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